LIBRARY ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity ComputeUnit is port ( Rst_n : in std_logic; Clock : in std_logic; LdIntReg : in std_logic; SelAdder : in std_logic; LdResultReg : in std_logic; ShiftData : in std_logic; LdIO : in std_logic; SelOne : in std_logic; Concat1 : in std_logic; LdSub : in std_logic; InputData : in unsigned (7 downto 0); IsZero : out std_logic; Smaller : out std_logic; result : out unsigned (5 downto 0) ); end ComputeUnit; architecture behav OF ComputeUnit IS component InputReg port ( LdIO : in std_logic; ShiftData : in std_logic; InputData : in unsigned (7 downto 0); Rst_n : in std_logic; Clock : in std_logic; IsZero : out std_logic; Bit8N7 : out unsigned (7 downto 6) ); end component; component IntReg port ( LdIntReg : in std_logic; SelAdder : in std_logic; Rst_n : in std_logic; Clock : in std_logic; Data : in unsigned(1 downto 0); Adder : in unsigned(5 downto 0); IntRegOut : out unsigned(7 downto 0) ); end component; component ResultReg port ( SelOne : in std_logic; LdResultReg : in std_logic; Concat1 : in std_logic; Rst_n : in std_logic; Clock : in std_logic; Data2Comparator : out unsigned(7 downto 0); Data2Adder : out unsigned(7 downto 0); result : out unsigned(5 downto 0) ); end component; component subtractor port ( Rst_n : in std_logic; Clock : in std_logic; LdSub : in std_logic; A : in unsigned (7 downto 0); B : in unsigned (7 downto 0); q : out unsigned (7 downto 0) ); end component; component comparator port ( A : in unsigned (7 downto 0); B : in unsigned (7 downto 0); q : out std_logic ); end component; signal Sub_InB, IntRegOut, Comp_InB, Sub_out : unsigned(7 downto 0); signal Bit8N7 : unsigned(1 downto 0); BEGIN -- behav subtract : subtractor port map ( Rst_n => Rst_n, Clock => Clock, LdSub => LdSub, A => IntRegOut, B => Sub_InB, q => Sub_out ); compare : comparator port map ( A => IntRegOut, B => Comp_InB, q => Smaller ); ResReg : ResultReg port map ( SelOne => SelOne, LdResultReg => LdResultReg, Concat1 => Concat1, Rst_n => Rst_n, Clock => Clock, Data2Comparator => Comp_InB, Data2Adder => Sub_InB, result => result ); IntReg1 : IntReg port map ( LdIntReg => LdIntReg, SelAdder => SelAdder, Rst_n => Rst_n, Clock => Clock, Data => Bit8N7, Adder => Sub_out(5 downto 0), IntRegOut => IntRegOut ); InputReg1 : InputReg port map ( LdIO => LdIO, ShiftData => ShiftData, InputData => InputData, Rst_n => Rst_n, Clock => Clock, IsZero => IsZero, Bit8N7 => Bit8N7 ); END behav;