Project part 1.
Display interface using SRAM as Video Memory require the following modules. The module names are listed below.

	VGADisplayFromSRAM_Top 	Module 
        vga_synch 		Module
	DCM 200MHz Instantiation
	BlockRAM Instantiation
	sram_ctrl Module
	debounce Module
	disp_hex_mux 
	Userconstraints file

Note : DCM and Block RAM are generated by core gen feature of xilinx ISE. The steps for generation are explained in the report.

Project Part 2

Connected Component Labeling Alorithm hdl implementation require the following modules
	  FIFO
	  CCL_PROC Module
	  serial_divide_uu Module

Individual .v files are sent.
In addition to these the code is available in CodeListing.txt