# Test disjoint sharp operation on two array of cubes # Chen, Qihong, 3/29/98 # 1 # var5c set conf 000000000 enable enififoa set addrb 0 disable enififoa enable enififod set water 00000 set right 11111 set prpo 1-1110-10-0-0101--0-0100-01-0-0000 ; disjoint sharp [D] #d [A] set inst 11-1-0-0-0100-0101-0100-0001 ; disjoint sharp [D] #d [A] set accu 10-10-10-10-10 ; cube B1 set conf 001000001 ; write result to MEM_B enable enIluB #disable MemBRW exec 11-11-11-11-11 ; cube 1 disable enIluB enable enaddrb ; [AddrB] => [AddrR] set addrr 0 ; operand 0 is useless but required disable enaddrb enable enIFifoA set addrb 0 disable enIFifoA set accu 10-10-10-01-01 ; cube B2 disable enIFifoD set conf 011101001 ; memB=>ILU=>memA enable MemBRW #disable MemARW enable enIluA loop 0 disable MemBRW disable enIluA # enable enaddra ; [AddrA] => [AddrR] set addrr 0 disable enaddra enable enIFifoA set addra 0 set addrb 0 disable enIFifoA enable enIFifoD set accu 10-10-01-01-10 ; cube B3 disable enIFifoD set conf 011000001 ; memA=>ILU=>memB enable MemARW #disable MemBRW enable enIluB loop 0 disable MemARW disable enIluB # enable enaddrb ; [AddrB] => [AddrR] set addrr 0 disable enaddrb enable enIFifoA set addrb 0 set addra 0 disable enIFifoA enable enIFifoD set accu 10-10-01-10-01 ; cube B4 disable enIFifoD set conf 011101001 ; memB=>ILU=>memA enable MemBRW #disable MemARW enable enIluA loop 0 disable MemBRW disable enIluA # enable enaddra ; [AddrA] => [AddrR] set addrr 0 disable enaddra enable enIFifoA set addra 0 set addrb 0 disable enIFifoA enable enIFifoD set accu 10-01-10-10-01 ; cube B5 disable enIFifoD set conf 011000001 ; memA=>ILU=>memB enable MemARW #disable MemBRW enable enIluB loop 0 disable MemARW disable enIluB # enable enaddrb ; [AddrB] => [AddrR] set addrr 0 disable enaddrb enable enIFifoA set addrb 0 set addra 0 disable enIFifoA enable enIFifoD set accu 10-01-10-01-10 ; cube B6 disable enIFifoD set conf 011101001 ; memB=>ILU=>memA enable MemBRW #disable MemARW enable enIluA loop 0 disable MemBRW disable enIluA # enable enaddra ; [AddrA] => [AddrR] set addrr 0 disable enaddra enable enIFifoA set addra 0 set addrb 0 disable enIFifoA enable enIFifoD set accu 10-01-01-01-01 ; cube B7 disable enIFifoD set conf 011000001 ; memA=>ILU=>memB enable MemARW #disable MemBRW enable enIluB loop 0 disable MemARW disable enIluB # enable enaddrb ; [AddrB] => [AddrR] set addrr 0 disable enaddrb enable enIFifoA set addrb 0 set addra 0 disable enIFifoA enable enIFifoD set accu 10-01-01-10-10 ; cube B8 disable enIFifoD set conf 011101001 ; memB=>ILU=>memA enable MemBRW #disable MemARW enable enIluA loop 0 disable MemBRW disable enIluA # enable enaddra ; [AddrA] => [AddrR] set addrr 0 disable enaddra enable enIFifoA set addra 0 set addrb 0 disable enIFifoA enable enIFifoD set accu 01-01-10-10-10 ; cube B9 disable enIFifoD set conf 011000001 ; memA=>ILU=>memB enable MemARW #disable MemBRW enable enIluB loop 0 disable MemARW disable enIluB # enable enaddrb ; [AddrB] => [AddrR] set addrr 0 disable enaddrb enable enIFifoA set addrb 0 set addra 0 disable enIFifoA enable enIFifoD set accu 01-01-10-01-01 ; cube B10 disable enIFifoD set conf 011101001 ; memB=>ILU=>memA enable MemBRW #disable MemARW enable enIluA loop 0 disable MemBRW disable enIluA # enable enaddra ; [AddrA] => [AddrR] set addrr 0 disable enaddra enable enIFifoA set addra 0 set addrb 0 disable enIFifoA enable enIFifoD set accu 01-01-01-01-10 ; cube B11 disable enIFifoD set conf 011000001 ; memA=>ILU=>memB enable MemARW #disable MemBRW enable enIluB loop 0 disable MemARW disable enIluB # enable enaddrb ; [AddrB] => [AddrR] set addrr 0 disable enaddrb enable enIFifoA set addrb 0 set addra 0 disable enIFifoA enable enIFifoD set accu 01-01-01-10-01 ; cube B12 disable enIFifoD set conf 011101001 ; memB=>ILU=>memA enable MemBRW #disable MemARW enable enIluA loop 0 disable MemBRW disable enIluA # enable enaddra ; [AddrA] => [AddrR] set addrr 0 disable enaddra enable enIFifoA set addra 0 set addrb 0 disable enIFifoA enable enIFifoD set accu 01-10-10-10-01 ; cube B13 disable enIFifoD set conf 011000001 ; memA=>ILU=>memB enable MemARW #disable MemBRW enable enIluB loop 0 disable MemARW disable enIluB # enable enaddrb ; [AddrB] => [AddrR] set addrr 0 disable enaddrb enable enIFifoA set addrb 0 set addra 0 disable enIFifoA enable enIFifoD set accu 01-10-10-01-10 ; cube B14 disable enIFifoD set conf 011101001 ; memB=>ILU=>memA enable MemBRW #disable MemARW enable enIluA loop 0 disable MemBRW disable enIluA # enable enaddra ; [AddrA] => [AddrR] set addrr 0 disable enaddra enable enIFifoA set addra 0 set addrb 0 disable enIFifoA enable enIFifoD set accu 01-10-01-01-01 ; cube B15 disable enIFifoD set conf 011000001 ; memA=>ILU=>memB enable MemARW #disable MemBRW enable enIluB loop 0 disable MemARW disable enIluB # enable enaddrb ; [AddrB] => [AddrR] set addrr 0 disable enaddrb enable enIFifoA set addrb 0 set addra 0 disable enIFifoA enable enIFifoD set accu 01-10-01-10-10 ; cube B16 disable enIFifoD set conf 011101001 ; memB=>ILU=>memA enable MemBRW #disable MemARW enable enIluA loop 0 disable MemBRW disable enIluA # enable enaddra ; [AddrA] => [AddrR] set addrr 0 disable enaddra enable enIFifoA set addra 0 set addrb 0 disable enIFifoA enable enIFifoD set accu 10-10-10-10-01 ; cube B17 disable enIFifoD set conf 011000001 ; memA=>ILU=>memB enable MemARW #disable MemBRW enable enIluB loop 0 disable MemARW disable enIluB # enable enaddrb ; [AddrB] => [AddrR] set addrr 0 disable enaddrb enable enIFifoA set addrb 0 set addra 0 disable enIFifoA enable enIFifoD set accu 10-10-10-01-10 ; cube B18 disable enIFifoD set conf 011101001 ; memB=>ILU=>memA enable MemBRW #disable MemARW enable enIluA loop 0 disable MemBRW disable enIluA # enable enaddra ; [AddrA] => [AddrR] set addrr 0 disable enaddra enable enIFifoA set addra 0 set addrb 0 disable enIFifoA enable enIFifoD set accu 10-10-01-01-01 ; cube B19 disable enIFifoD set conf 011000001 ; memA=>ILU=>memB enable MemARW #disable MemBRW enable enIluB loop 0 disable MemARW disable enIluB # enable enaddrb ; [AddrB] => [AddrR] set addrr 0 disable enaddrb enable enIFifoA set addrb 0 set addra 0 disable enIFifoA enable enIFifoD set accu 10-10-01-10-10 ; cube B20 disable enIFifoD set conf 011101001 ; memB=>ILU=>memA enable MemBRW #disable MemARW enable enIluA loop 0 disable MemBRW disable enIluA # enable enaddra ; [AddrA] => [AddrR] set addrr 0 disable enaddra enable enIFifoA set addra 0 set addrb 0 disable enIFifoA enable enIFifoD set accu 10-01-10-10-10 ; cube B21 disable enIFifoD set conf 011000001 ; memA=>ILU=>memB enable MemARW #disable MemBRW enable enIluB loop 0 disable MemARW disable enIluB # enable enaddrb ; [AddrB] => [AddrR] set addrr 0 disable enaddrb enable enIFifoA set addrb 0 set addra 0 disable enIFifoA enable enIFifoD set accu 10-01-10-01-01 ; cube B22 disable enIFifoD set conf 011101001 ; memB=>ILU=>memA enable MemBRW #disable MemARW enable enIluA loop 0 disable MemBRW disable enIluA # enable enaddra ; [AddrA] => [AddrR] set addrr 0 disable enaddra enable enIFifoA set addra 0 set addrb 0 disable enIFifoA enable enIFifoD set accu 10-01-01-01-10 ; cube B23 disable enIFifoD set conf 011000001 ; memA=>ILU=>memB enable MemARW #disable MemBRW enable enIluB loop 0 disable MemARW disable enIluB # enable enaddrb ; [AddrB] => [AddrR] set addrr 0 disable enaddrb enable enIFifoA set addrb 0 set addra 0 disable enIFifoA enable enIFifoD set accu 10-01-01-10-01 ; cube B24 disable enIFifoD set conf 011101001 ; memB=>ILU=>memA enable MemBRW #disable MemARW enable enIluA loop 0 disable MemBRW disable enIluA # enable enaddra ; [AddrA] => [AddrR] set addrr 0 disable enaddra enable enIFifoA set addra 0 set addrb 0 disable enIFifoA enable enIFifoD set accu 01-01-10-10-01 ; cube B25 disable enIFifoD set conf 011000001 ; memA=>ILU=>memB enable MemARW #disable MemBRW enable enIluB loop 0 disable MemARW disable enIluB # enable enaddrb ; [AddrB] => [AddrR] set addrr 0 disable enaddrb enable enIFifoA set addrb 0 set addra 0 disable enIFifoA enable enIFifoD set accu 01-01-10-01-10 ; cube B26 disable enIFifoD set conf 011101001 ; memB=>ILU=>memA enable MemBRW #disable MemARW enable enIluA loop 0 disable MemBRW disable enIluA # enable enaddra ; [AddrA] => [AddrR] set addrr 0 disable enaddra enable enIFifoA set addra 0 set addrb 0 disable enIFifoA enable enIFifoD set accu 01-01-01-01-01 ; cube B27 disable enIFifoD set conf 011000001 ; memA=>ILU=>memB enable MemARW #disable MemBRW enable enIluB loop 0 disable MemARW disable enIluB # enable enaddrb ; [AddrB] => [AddrR] set addrr 0 disable enaddrb enable enIFifoA set addrb 0 set addra 0 disable enIFifoA enable enIFifoD set accu 01-01-01-10-10 ; cube B28 disable enIFifoD set conf 011101001 ; memB=>ILU=>memA enable MemBRW #disable MemARW enable enIluA loop 0 disable MemBRW disable enIluA # enable enaddra ; [AddrA] => [AddrR] set addrr 0 disable enaddra enable enIFifoA set addra 0 set addrb 0 disable enIFifoA enable enIFifoD set accu 01-10-10-10-10 ; cube B29 disable enIFifoD set conf 011000001 ; memA=>ILU=>memB enable MemARW #disable MemBRW enable enIluB loop 0 disable MemARW disable enIluB # enable enaddrb ; [AddrB] => [AddrR] set addrr 0 disable enaddrb enable enIFifoA set addrb 0 set addra 0 disable enIFifoA enable enIFifoD set accu 01-10-10-01-01 ; cube B30 disable enIFifoD set conf 011101001 ; memB=>ILU=>memA enable MemBRW #disable MemARW enable enIluA loop 0 disable MemBRW disable enIluA # enable enaddra ; [AddrA] => [AddrR] set addrr 0 disable enaddra enable enIFifoA set addra 0 set addrb 0 disable enIFifoA enable enIFifoD set accu 01-10-01-01-10 ; cube B31 disable enIFifoD set conf 011000001 ; memA=>ILU=>memB enable MemARW #disable MemBRW enable enIluB loop 0 disable MemARW disable enIluB ## last one enable enaddrb ; [AddrB] => [AddrR] set addrr 0 disable enaddrb enable enIFifoA set addrb 0 #set addra 0 disable enIFifoA enable enIFifoD set accu 01-10-01-10-01 ; cube B32 disable enIFifoD set conf 101101100 ; memB=>ILU=>OFifo enable MemBRW loop 0