library ieee;
use std.textio.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity testram is
end testram;

architecture test of testram is

constant memsize : integer := 16;
constant awidth : integer := 8;
constant dwidth : integer := 8;

component ram 
  generic
   ( Size     : integer := 64;    -- number of memory words
     AddrWidth: integer := 8;     -- number of address bits
     DataWidth: integer := 8;     -- number of bits per memory word
     download_on_power_up: boolean := true;
               -- if TRUE, RAM is downloaded at start of simulation
     download_filename: IN string := "ram_data.txt"
   );
  port
   ( ce : in std_logic;              -- Chip-Enable
     memread, memwrite: in std_logic;      -- read and write commands
     clk: in std_logic;              -- clock for write operation
     addr : in std_logic_vector (AddrWidth-1 downto 0);
     dbus : inout std_logic_vector (DataWidth-1 downto 0);
     dump: in std_logic := '0';
        -- 0-to-1 transaction downloads the content of memory
        -- (dump_start to dump_end) to the log file
     dump_start: in integer := 0;
     dump_end:   in integer := Size-1
   );
end component;

signal ce, memread, memwrite, dump: std_logic;
signal clk: std_logic := '0';
signal dump_start : integer := 0;
signal dump_end   : integer := memsize-1;
signal addr : std_logic_vector (awidth-1 downto 0);
signal dbus : std_logic_vector (dwidth-1 downto 0);
signal simulation_done : boolean := false;

BEGIN

  u0: ram
      generic map 
       (Size=>memsize, AddrWidth=>awidth, DataWidth=>dwidth)
      port map
       (ce=>ce, memread=>memread, memwrite=>memwrite, clk=>clk,
        dump=>dump, dump_start=>dump_start, dump_end=>dump_end,
        addr=>addr, dbus=>dbus);

  clock: process 
  begin
    clk <= not clk after 50 ns;
    wait for 50 ns;
  end process;

  verify: process
    variable outbuf: line;
  begin
    write(outbuf, string'("Initialize ... "));
    writeline(output, outbuf);
    ce <= '1';
    memread <= '0';
    memwrite <= '0';
    dump <= '0';
    addr <= (others => '0');
    dbus <= (others => 'Z');

    wait for 100 ns;
    write(outbuf, string'("Dump Test 1 ... "));
    writeline(output, outbuf);
    dump <= '1';

    wait for 100 ns;
    dump <= '0';
    memread <= '1';
    addr <= "00001111";
    
    wait for 100 ns;
    write(outbuf, string'("Read Memory [15] = "));
    write(outbuf, dbus);
    writeline(output, outbuf);

    memread <= '0';
    wait for 100 ns;

    memwrite <= '1';
    dbus <= "10101010";
    wait for 100 ns;
    write(outbuf, string'("Write Memory [15] = "));
    write(outbuf, dbus);
    writeline(output, outbuf);

    write(outbuf, string'("Dump Test 2 ... "));
    writeline(output, outbuf);
    dump_start <= 10;
    dbus <= (others => 'Z');
    dump <= '1';
    wait for 100 ns;

    simulation_done <= true;

  end process;

END;