library ieee;
use ieee.std_logic_1164.all;

entity testempty is
end;

architecture dataflow of testempty is

component it_empty
  port (c : in std_logic_vector (0 to 1);
        redge_pre, redge, water : in std_logic;
        empty_pre : in std_logic;
        empty_nxt, empty : out std_logic);
end component;

signal c : std_logic_vector(0 to 5);
signal empty_carry, redge : std_logic_vector(0 to 3);
signal empty, water : std_logic_vector(1 to 3);
signal emptyflag : std_logic;

begin

  redge(0) <= '1';

  u1: it_empty port map
   ( c=>c(0 to 1), redge_pre=>redge(0), redge=>redge(1),
     water=>water(1),
     empty_pre=>empty_carry(0), empty_nxt=>empty_carry(1),
     empty=>empty(1)
   ); 

  u2: it_empty port map
   ( c=>c(2 to 3), redge_pre=>redge(1), redge=>redge(2),
     water=>water(2),
     empty_pre=>empty_carry(1), empty_nxt=>empty_carry(2),
     empty=>empty(2)
   ); 

  u3: it_empty port map
   ( c=>c(4 to 5), redge_pre=>redge(2), redge=>redge(3),
     water=>water(3),
     empty_pre=>empty_carry(2), empty_nxt=>empty_carry(3),
     empty=>empty(3)
   ); 

  emptyflag <= empty(1) or empty(2) or empty(3);

end dataflow;