library ieee; use ieee.std_logic_1164.all; use std.textio.all; package stringpkg is procedure get_string(L:inout line; VALUE:out line; GOOD: out boolean); procedure cmp_string(a: inout line; b: in string; equal: out boolean); procedure read_std_logic_vector (L: inout line; vec: inout std_logic_vector; fill: in std_logic); end stringpkg; package body stringpkg is procedure skip_white(variable L : in LINE; pos : inout integer) is begin while pos <= L'high loop case L(pos) is when ' ' | HT => pos := pos + 1; when others => exit; end case; end loop; end skip_white; procedure get_string(L:inout line; VALUE:out line; GOOD: out boolean) IS variable old_L : line := L; variable pos, start_pos : integer; variable findwhite : boolean := false; begin if (L = null) then GOOD := false; else pos := L'low; skip_white(L, pos); start_pos := pos; -- read string until first white space if (pos <= L'high) then GOOD := true; while pos <= L'high loop case L(pos) is when ' ' | HT => findwhite := true; exit; when others => if (pos /= L'high) then pos := pos + 1; else exit; end if; end case; end loop; if findwhite then VALUE := new string'(L(start_pos to pos-1)); else VALUE := new string'(L(start_pos to pos)); end if; if (pos = L'high) then L := null; else L := new string'(old_L(pos+1 to old_L'high)); end if; Deallocate(old_L); else L := null; Deallocate(old_L); VALUE := null; GOOD := false; end if; end if; end get_string; function lower_case(c : character) return character is begin if c >= 'A' and c <= 'Z' then return character'val(character'pos(c) + 32); else return c; end if; end; procedure cmp_string(a: inout line; b: in string; equal: out boolean) is variable a_char, b_char : character; variable s,s2, e,e2 : integer; begin if (a = null) then equal := false; elsif a'length /= b'length then equal := false; else for i in 0 to a'length-1 loop a_char := lower_case(a(a'low+i)); b_char := lower_case(b(b'low+i)); if a_char /= b_char then equal := false; exit; else equal := true; end if; end loop; end if; end cmp_string; procedure read_std_logic_vector (L: inout line; vec: inout std_logic_vector; fill: in std_logic) is alias val: std_logic_vector(1 to vec'length) is vec; variable old_L : LINE := L; variable lpos, vpos: integer := 0; begin if L /= null then lpos := L'low; skip_white(L, lpos); while lpos <= L'high and vpos < vec'length loop if L(lpos) = '0' then vpos := vpos + 1; val(vpos) := '0'; elsif L(lpos) = '1' then vpos := vpos + 1; val(vpos) := '1'; elsif L(lpos) /= '-' then exit; -- Bit values must be '0' or '1'. end if; lpos := lpos + 1; end loop; end if; if vpos < vec'length then while vpos < vec'length loop vpos := vpos + 1; val(vpos) := fill; end loop; end if; if lpos>1 then L := new string'(old_L(lpos to old_L'high)); Deallocate(old_L); end if; end read_std_logic_vector; end stringpkg;