library ieee;
use ieee.std_logic_1164.all;
use work.all;
use work.parts.all;

entity reg8 is
  port (d: in std_logic_vector (7 downto 0);
        load, reset: in std_logic;
        q: out std_logic_vector (7 downto 0));
end;

architecture behavior of reg8 is
begin
  u1: parts.regn generic map(8) port map (d=>d, load=>load, reset=>reset, q=>q);
end behavior;