Cube Calculus Machine II VHDL model

The architecture of CCM2 is described in my thesis. For understanding this VHDL
model, you should read my thesis first. Please keep it in mind, my thesis is 
not the design documentation of CCM2, it only give you main idea that how the
CCM2 works. If you don't understand how CCM2 works, don't bother try to 
understand this VHDL model. You will find that a lot of signals are not 
described in the thesis, most of them are tempory signals/variables, and they 
are required by VHDL syntax, not by CCM2 design.

The components of IT are described by the following VHDL files: it_oper.vhd
(the operation block), it_state.vhd (the state block), it_ident.vhd (the 
identify block), it_empty.vhd (the empty block), and it_count.vhd (the counter
block). The IT cell is described by itcell.vhd (see figure 3.11 of the thesis).

The ILU described in this VHDL model includes ILU and OCU described in the
thesis. The OCU is called "the control unit of ILU"  at first, then it is
renamed as OCU. In this VHDL model, OCU is described by ilu_cu.vhd. The ILU
(integrated OCU part) is described by ilu.vhd.

The GCU is described by biu.vhd (it was called Bus Interface Unit, BIU for
short). The finite state machine part is described by biu_cu.vhd.