library ieee;
use std.textio.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

----------------------------------------------------------------------------
-- This function block describes a simple model of RAM.
----------------------------------------------------------------------------

entity ram is
  generic 
   ( Size     : integer := 64;    -- number of memory words
     AddrWidth: integer := 8;     -- number of address bits
     DataWidth: integer := 8;     -- number of bits per memory word
     download_on_power_up: boolean := true;
               -- if TRUE, RAM is downloaded at start of simulation
     download_filename: IN string := "ram_data.txt"
   );
  port 
   ( ce : in std_logic;              -- Chip-Enable 
     memread, memwrite: in std_logic;      -- read and write commands
     clk: in std_logic;              -- clock for write operation
     addr : in std_logic_vector (AddrWidth-1 downto 0);
     dbus : inout std_logic_vector (DataWidth-1 downto 0);
     dump : in std_logic; 
        -- 0-to-1 transaction downloads the content of memory 
        -- (dump_start to dump_end) to the log file
     dump_start: in integer; 
     dump_end:   in integer
   );
end;

architecture behavior of ram is

type memory is array (0 to Size-1) of std_logic_vector (DataWidth-1 downto 0);

begin

  memory_process: process (ce, memread, memwrite, clk, addr, dbus, dump)
  variable init_done: boolean := false;
  variable mem: memory;

  function stdvec2int(stdvec: std_logic_vector) return integer is
  variable result : integer := 0;
  begin
    for i in stdvec'range loop
      result := result * 2;
      if (stdvec(i) = '1') then
        result := result + 1;
      end if;
    end loop;
    return result;
  end;

  procedure load_mem is
    file infile: text is in download_filename;
    variable inbuf: line;
    variable outbuf: line;
    variable good : boolean;
    variable ch: character;
    variable iaddr: integer;
    variable ram_data: std_logic_vector(DataWidth-1 downto 0);
  begin
    write(outbuf,string'("Loading SRAM from file "));
    write(outbuf,download_filename & string'(" ... "));
    writeline (output, outbuf);
  
    while not endfile(infile) loop
      readline(infile, inbuf);
      read(inbuf, ch, good);
      if (not good) or (ch /= ' ') then next; end if;
      read(inbuf, iaddr);
      read(inbuf, ch);
      read(inbuf, ram_data);
      if (iaddr<Size) then
        mem(iaddr) := ram_data;
        write(outbuf, string'(" RAM["));   -- trace
        write(outbuf, iaddr);
        write(outbuf, string'("] :=  "));
        write(outbuf, mem(iaddr));
        writeline(output, outbuf);
      end if;
    end loop;
  end;

  procedure dump_mem is 
    variable outbuf: line;
  begin
      if (dump_start > dump_end)  or (dump_end >= Size) then
        assert false
        report "Invalid addresses for memory dump. Cancelled."
        severity error;
      else
        write(outbuf, string'("Memory dump ..."));
        writeline(output, outbuf);
        for i in dump_start to dump_end loop
          write(outbuf, string'(" RAM["));   -- trace
          write(outbuf, i);
          write(outbuf, string'("] :=  "));
          write(outbuf, mem(i));
          writeline(output, outbuf);
        end loop;
      end if;
  end;

  begin   -- memory process
    if (not init_done) then 
       for i in 0 to size-1 loop
         mem(i) := (others=>'X');
       end loop;
       
       if download_on_power_up then 
         load_mem;
       end if;

       init_done := true;
    end if;

    if ce = '0' then
       dbus <= (others => 'Z');
    else
      if (memread = '1' and memwrite = '1') then
        dbus <= (others => 'Z');
      elsif memread = '1' then
        if (stdvec2int(addr) < Size) then
          dbus <= mem(stdvec2int(addr));
        else
          dbus <= (others => 'X');
        end if;
      elsif memwrite = '1' then
        if clk = '1' and clk'event then
          if (stdvec2int(addr) < Size) then
            mem(stdvec2int(addr)) := dbus;
          end if;
        end if;
      else
          dbus <= (others => 'Z');
      end if;
    end if;

    if (dump = '1') and dump'event then 
       dump_mem;
    end if;

  end process;

end behavior;