library ieee; use ieee.std_logic_1164.all; ------------------------------------------------------- -- Declare all basic components. ------------------------------------------------------- package parts is component dff port (d, clk, reset : in std_logic; q : out std_logic); end component; component mux41 port (din: in std_logic_vector (0 to 3); sel: in std_logic_vector (1 downto 0); dout: out std_logic); end component; component mux441 port (din0: in std_logic_vector (0 to 3); din1: in std_logic_vector (0 to 3); din2: in std_logic_vector (0 to 3); din3: in std_logic_vector (0 to 3); sel: in std_logic_vector (1 downto 0); dout: out std_logic_vector (0 to 3)); end component; component regN generic (size: integer := 8); port (d: in std_logic_vector (size-1 downto 0); load, reset: in std_logic; q: out std_logic_vector (size-1 downto 0)); end component; component tbufN generic (size: integer := 8); port (din: in std_logic_vector (size-1 downto 0); en: in std_logic; dout: out std_logic_vector (size-1 downto 0)); end component; component counterN generic (size: integer := 4); port (clk, reset, ld, ce : in std_logic; d : in std_logic_vector(size-1 downto 0); q : out std_logic_vector(size-1 downto 0)); end component; component equalN generic (size: integer := 4); port (din0, din1: in std_logic_vector (Size-1 downto 0); o: out std_logic); end component; component decoder3to8 port (din: in std_logic_vector (2 downto 0); dout: out std_logic_vector (7 downto 0)); end component; component mux21N generic (size: integer := 4); port (din0, din1: in std_logic_vector (Size-1 downto 0); sel : in std_logic; dout: out std_logic_vector(Size-1 downto 0)); end component; component cmpN generic (size: integer := 4); port (dinA, dinB: in std_logic_vector (Size-1 downto 0); lt, eq, gt : out std_logic ); end component; end parts;