------------------------------------------------------- -- D flip-flop with asynchronous reset ------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity dff is port (d, clk, reset : in std_logic; q : out std_logic); end; architecture behavior of dff is begin process (d, clk, reset) begin if reset = '1' then q <= '0' after 1 ns; elsif clk = '1' and clk'event then q <= d after 1 ns; end if; end process; end behavior; ------------------------------------------------------- -- 1-bit 4 to 1 MUX ------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity mux41 is port (din: in std_logic_vector (0 to 3); sel: in std_logic_vector (1 downto 0); dout: out std_logic); end; architecture dataflow of mux41 is begin dout <= (din(0) and not(sel(1)) and not(sel(0))) or (din(1) and not(sel(1)) and sel(0) ) or (din(2) and sel(1) and not(sel(0))) or (din(3) and sel(1) and sel(0) ) after 3 ns; end dataflow; ------------------------------------------------------- -- 4-bit 4 to 1 MUX ------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity mux441 is port (din0: in std_logic_vector (0 to 3); din1: in std_logic_vector (0 to 3); din2: in std_logic_vector (0 to 3); din3: in std_logic_vector (0 to 3); sel: in std_logic_vector (1 downto 0); dout: out std_logic_vector (0 to 3)); end; architecture dataflow of mux441 is component mux41 port (din: in std_logic_vector (0 to 3); sel: in std_logic_vector (1 downto 0); dout: out std_logic); end component; signal u0din,u1din,u2din,u3din: std_logic_vector (0 to 3); begin u0din <= din0(0) & din1(0) & din2(0) & din3(0); u1din <= din0(1) & din1(1) & din2(1) & din3(1); u2din <= din0(2) & din1(2) & din2(2) & din3(2); u3din <= din0(3) & din1(3) & din2(3) & din3(3); U0: mux41 port map (din=>u0din, sel=>sel, dout=>dout(0)); U1: mux41 port map (din=>u1din, sel=>sel, dout=>dout(1)); U2: mux41 port map (din=>u2din, sel=>sel, dout=>dout(2)); U3: mux41 port map (din=>u3din, sel=>sel, dout=>dout(3)); end dataflow; ------------------------------------------------------- -- n-bit register with asynchronous reset ------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity regN is generic (size: integer := 8); port (d: in std_logic_vector (size-1 downto 0); load, reset: in std_logic; q: out std_logic_vector (size-1 downto 0)); end; architecture behavior of regN is begin process (load, reset) begin if reset = '1' then q <= (others => '0') after 2 ns; elsif load = '1' and load'event then q <= d after 2 ns; end if; end process; end behavior; ------------------------------------------------------- -- n-bit tri-state buffer ------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity tbufN is generic (size: integer := 8); port (din: in std_logic_vector (size-1 downto 0); en: in std_logic; dout: out std_logic_vector (size-1 downto 0)); end; architecture arch of tbufN is begin dout <= din when (en = '1') else (others => 'Z'); end arch; ------------------------------------------------------- -- n-bit loadable up-counter with asynchronous reset ------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity counterN is generic (size: integer := 4); port (clk, reset, ld, ce : in std_logic; d : in std_logic_vector(size-1 downto 0); q : out std_logic_vector(size-1 downto 0)); end counterN; architecture behavior of counterN is signal q_i: std_logic_vector(size-1 downto 0); begin process (reset,clk, ld, ce, d) begin if (reset = '1') then q_i <= (others=>'0'); elsif (clk = '1') and (clk'event) then if (ld = '1') then q_i <= d; elsif ( ce = '1') then q_i <= std_logic_vector(unsigned(q_i) + 1) ; end if; end if; end process; q <= q_i after 20 ns; end behavior; ------------------------------------------------------- -- N-bit equvalence comparator ------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity equalN is generic (size: integer := 4); port (din0, din1: in std_logic_vector (Size-1 downto 0); o: out std_logic); end; architecture behavior of equalN is begin o <= '1' when (din0 = din1) else '0' after 2 ns; end behavior; ------------------------------------------------------- -- 3 to 8 decoder ------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity decoder3to8 is port (din: in std_logic_vector (2 downto 0); dout: out std_logic_vector (7 downto 0)); end; architecture arch of decoder3to8 is begin dout <= "10000000" when (din = "111") else "01000000" when (din = "110") else "00100000" when (din = "101") else "00010000" when (din = "100") else "00001000" when (din = "011") else "00000100" when (din = "010") else "00000010" when (din = "001") else "00000001" when (din = "000") else "XXXXXXXX" after 3 ns; end arch; ------------------------------------------------------- -- N-bit 2-to-1 multiplexer ------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity mux21N is generic (size: integer := 4); port (din0, din1: in std_logic_vector (Size-1 downto 0); sel : in std_logic; dout: out std_logic_vector(Size-1 downto 0)); end; architecture arch of mux21N is begin dout <= din1 when (sel = '1') else din0 after 2 ns; end arch; ------------------------------------------------------- -- N-bit comparator ------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity cmpN is generic (size: integer := 4); port (dinA, dinB: in std_logic_vector (Size-1 downto 0); lt, eq, gt : out std_logic ); end; architecture arch of cmpN is begin lt <= '1' after 5 ns when (dinA < dinB) else '0' after 5 ns; eq <= '1' after 5 ns when (dinA = dinB) else '0' after 5 ns; gt <= '1' after 5 ns when (dinA > dinB) else '0' after 5 ns; end arch;