-- IT cell
--
-- Signals:
--   bef: 4 bits output value of before function.
--   act: 4 bits output value of active function.
--   aft: 4 bits output value of after function.
--   rel: 4 bits output value of partial relation function.
--   a: two bits from operand literal A.
--   b: two bits from operand literal B.
--   c: two bits of the output literal.
--   and_or: and_or signal
--   redge: re[i], right edge signal
--   redge_pre: re[i-1], right edge signal
--   water: w[i], water signal
--   reset: global reset. this signal can be seen as chip reset.
--   request: the clock signal of FSM of the IT
--   clear: used to reset IT to "before" state.
--   prime: prime signal
--   nxt: next[i] signal ("next" is a reserved word in VHDL).
--   nxt_nxt: next[i+1] signal.
--   carry: carry[i], carry signal
--   carry_nxt: carry[i+1], carry signal
--   conf: conf[i], confirm signal
--   conf_pre: conf[i-1], confirm signal
--   ready: subready[i], ready signal of the IT
--   empty_pre: empty_carry[i], empty carry signal
--   empty_nxt: empty_carry[i+1], empty carry signal
--   empty: subempty[i], empty signal
--   cnt_in: cnt[i], counter carry signal
--   cnt_out: cnt[i+1], counter carry signal
--   count: count[i], count signal

library ieee;
use ieee.std_logic_1164.all;
use work.all;
use work.parts.all;

entity itcell is
  port (rel, bef, act, aft: in std_logic_vector (0 to 3);
        a, b: in std_logic_vector (0 to 1);
        and_or, redge, redge_pre, water: in std_logic;
        reset, request, clear, prime: in std_logic;
        nxt,     carry,     conf    : in std_logic;  -- propagation signals
        nxt_nxt, carry_nxt, conf_pre: out std_logic; -- propagation signals
        ready: out std_logic;
        c: out std_logic_vector (0 to 1);
        empty_pre : in std_logic;
        empty_nxt, empty : out std_logic;
        cnt_in : in std_logic_vector (3 downto 0);
        cnt_out : out std_logic_vector (3 downto 0);
        count : out std_logic );
end;

architecture dataflow of itcell is

component it_operation
  port (bef,act,aft: in  std_logic_vector (0 to 3);
        state:       in  std_logic_vector (1 downto 0);
        a,b:         in  std_logic_vector (0 to 1);
        c:           out std_logic_vector (0 to 1));
end component;

component it_state
  port (clear, request, reset, prime: in std_logic;
        nxt, var, water, redge: in std_logic;
        state: out std_logic_vector (1 downto 0);
        nxt_nxt, ready: out std_logic);
end component;

component it_identify
  port (rel: in  std_logic_vector (0 to 3);
        a, b: in  std_logic_vector (0 to 1);
        and_or, water:    in std_logic;
        redge, redge_pre: in std_logic;
        carry, conf:      in std_logic;
        carry_nxt, conf_pre, var: out std_logic;
        count : out std_logic );
end component;

component it_empty
  port (c : in std_logic_vector (0 to 1);
        redge_pre, redge, water : in std_logic;
        empty_pre : in std_logic;
        empty_nxt, empty : out std_logic);
end component;

component it_count
  port (cnt_in  : in std_logic_vector (3 downto 0);
        count   : in std_logic;
        cnt_out : out std_logic_vector (3 downto 0));
end component;

-- state: state[i], state signal of FSM within the IT
signal state : std_logic_vector (1 downto 0);

-- var: var[i], variable signal
-- tmp_count signal is the count signal. 
signal var, tmp_count : std_logic;
-- c_tmp signal is the c signal (the output literal)
signal c_tmp : std_logic_vector (0 to 1);

begin

  U0: it_identify port map
      (rel=>rel, and_or=>and_or, a=>a, b=>b,
       water=>water, redge=>redge, redge_pre=>redge_pre,
       carry=>carry, carry_nxt=>carry_nxt,
       conf=>conf, conf_pre=>conf_pre, var=>var, count=>tmp_count);

  U1: it_state port map
      (clear=>clear, request=>request, reset=>reset, prime=>prime, 
       nxt=>nxt, var=>var, water=>water, redge=>redge, 
       state=>state, nxt_nxt=>nxt_nxt, ready=>ready);

  U2: it_operation port map
      (bef=>bef, act=>act, aft=>aft, state=>state, 
       a=>a, b=>b, c=>c_tmp);

  c <= c_tmp;

  U3: it_empty port map
      (c=>c_tmp, redge_pre=>redge_pre, redge=>redge, water=>water,
       empty_pre=>empty_pre, empty_nxt=>empty_nxt, empty=>empty);

  U4: it_count port map
      (cnt_in=>cnt_in, count=>tmp_count, cnt_out=>cnt_out);

  count <= tmp_count;

end dataflow;