-- The state block of IT cell
-- 
-- Signals:
--   clear: used to reset IT to "before" state.
--   request: the clock signal of FSM of the IT
--   reset: global reset. this signal can be seen as chip reset.
--   prime: prime signal
--   nxt: next[i] signal ("next" is a reserved word in VHDL).
--   nxt_nxt: next[i+1] signal.
--   var: var[i], variable signal
--   water: w[i], water signal
--   redge: re[i], right edge signal
--   state: state signal
--   ready: subready[i], ready signal of the IT
  
library ieee;
use ieee.std_logic_1164.all;
use work.all;
use work.parts.all;

entity it_state is
  port (clear, request, reset, prime: in std_logic;  -- global signals
        nxt, var, water, redge: in std_logic;
        state: out std_logic_vector (1 downto 0);
        nxt_nxt, ready: out std_logic);
end;

architecture dataflow of it_state is

signal st1, st0 : std_logic;   -- current state 
signal nst1, nst0: std_logic;  -- next state
signal dff_reset: std_logic;

begin

  dff_reset <= reset or clear;

  U0: parts.dff port map 
    (d=>nst0, clk=>request, reset=>dff_reset, q=>st0);
  
  U1: parts.dff port map 
    (d=>nst1, clk=>request, reset=>dff_reset, q=>st1);
  
  nst0 <= (not st1) and (not st0) and (not clear) and nxt and var after 3 ns;
  nst1 <= st0 or st1 or  (nxt and (not var)) after 3 ns;

  state(1) <= st1;
  state(0) <= st0 or (var and prime) after 1 ns;

  nxt_nxt <= (nxt and water) or
             ((not water) and 
             (((not st1) and st0) or (nxt and (not (var and redge)))))
             after 3 ns;

  ready <= redge and nxt and var and (not request) after 3 ns;

end dataflow;