-- The operation block of IT cell
--
-- Signals: 
--   bef: 4 bits output value of before function.
--   act: 4 bits output value of active function.
--   aft: 4 bits output value of after function.
--     a: two bits from operand literal A.
--     b: two bits from operand literal B.
--     c: two bits of the output literal.
--   state: state of the IT, comes from state block.  

library ieee;
use ieee.std_logic_1164.all;
use work.all;
use work.parts.all;

entity it_operation is
  port (bef,act,aft: in  std_logic_vector (0 to 3);
        state:       in  std_logic_vector (1 downto 0);
        a,b:         in  std_logic_vector (0 to 1);
        c:           out std_logic_vector (0 to 1));
end;

architecture dataflow of it_operation is

-- temp signals.
signal u0sel,u1sel: std_logic_vector (1 downto 0);
signal bus4, fourzero: std_logic_vector (0 to 3);

begin

  fourzero <= "0000";

  U0: parts.mux441 port map 
     (din0=>bef, din1=>act, din2=>aft, din3=>fourzero, sel=>state, dout=>bus4);

  u0sel <= a(0) & b(0);
  U1: parts.mux41 port map (din=>bus4, sel=>u0sel, dout=>c(0));

  u1sel <= a(1) & b(1);
  U2: parts.mux41 port map (din=>bus4, sel=>u1sel, dout=>c(1));

end dataflow;