-- The identify block of IT.
--
-- Signals:
--   rel: 4 bits output value of partial relation function.
--   a: two bits from operand literal A.
--   b: two bits from operand literal B.
--   and_or: and_or signal
--   redge: re[i], right edge signal
--   redge_pre: re[i-1], right edge signal
--   water: w[i], water signal
--   carry: carry[i], carry signal
--   carry_nxt: carry[i+1], carry signal
--   conf: conf[i], confirm signal
--   conf_pre: conf[i-1], confirm signal
--   count: count[i], count signal

library ieee;
use ieee.std_logic_1164.all;
use work.all;
use work.parts.all;

entity it_identify is
  port( rel: in  std_logic_vector (0 to 3);
        a, b: in  std_logic_vector (0 to 1);
        and_or, water:    in std_logic;
        redge, redge_pre: in std_logic;
        carry, conf:      in std_logic;
        carry_nxt, conf_pre, var: out std_logic;
        count : out std_logic
      );
end;

architecture dataflow of it_identify is

signal u0sel, u1sel: std_logic_vector (1 downto 0);
signal rel0, rel1, i_carry_nxt, i_conf_pre, i_var: std_logic;

begin

  u0sel <= a(0) & b(0);
  U0: parts.mux41 port map (din=>rel, sel=>u0sel, dout=>rel0);

  u1sel <= a(1) & b(1);
  U1: parts.mux41 port map (din=>rel, sel=>u1sel, dout=>rel1);

  i_carry_nxt <= ((not water) 
                    and (   (rel0 and rel1 and redge_pre)
                         or (rel0 and rel1 and carry)
                         or (carry and (not redge_pre) and (not and_or))
                         or ((rel0 or rel1) and (not and_or))
                        ) 
                 )
              or (water and carry) after 2 ns;

  i_conf_pre <= (i_carry_nxt and redge) or (conf and (not redge)) after 2 ns;

  i_var <= i_conf_pre and (not water) after 2 ns;

  carry_nxt <= i_carry_nxt;

  conf_pre <= i_conf_pre;

  count <= i_var and redge and (not water) after 2 ns;

  var <= i_var;

end dataflow;