-- File:   ilu_cu.vhd  
-- Author: CHEN, Qihong,  Portland State University
-- Date:   12/9/97
--
-- The control unit of ILU (OCU in the thesis)
--
-- Signals:
--   reset: global reset. this signal can be seen as chip reset.
--   clk: global clock signal.
--   enable: ilu_enable signal in the thesis.
--   done: ilu_done signal in the thesis.
--   init: next[1], first next signal
--   term: next[n+1], last next signal.
--   ready: ready signal
--   to_mem: toMem signal, one bit of config register.
--   clear: used to reset all ITs to "before" state.
--   request: the clock signal of FSM of the IT
--   write_output: this signal is generated when there is a resultant cube.
--   inc_waddr: this signal used to increase mem address unit by 1.
--
--  The section 3.6 of the thesis give a brief introduction to this finite
--  state machine. The OCU is only used to deal with sequential cube operation.
--  The ilu_enable (enable in the VHDL code) will be 0 when the CCM is used to
--  carry out the combinational cube operation (including complex combinational
--  cube operation). In this case, the clear signal is set to 1 (in state st0)
--  to keep all ITs in "before" state. 

library ieee;
use ieee.std_logic_1164.all;

entity ilu_cu is
  port (reset, clk, enable, ready, term, to_mem: in std_logic;
        clear, request, init, write_output, inc_waddr, done: out std_logic );
end;

architecture behavior of ilu_cu is

  -- In figure 3.17 of the thesis, the states of OCU are s0 to s5, and they
  -- are corresponding to st0 ... st5, respectively.
  type ILUstate is (st0, st1, st2, st3, st4, st5);
              
  signal present_state, next_state: ILUstate;

begin

  
  state_clocked: process (clk) 
  begin
    if (clk'event and clk='1') then
       present_state <= next_state;
    end if;
  end process state_clocked;

  state_comb: process (present_state, enable, reset, ready, term)
  begin

    if (reset = '1') then

       next_state <= st0;

    else

       case present_state is

         when st0 =>

           if (enable  = '1') then
              next_state <= st1;
           else
              next_state <= st0;
           end if;

           clear         <= '1';
           request       <= '0';
           init          <= '0';
           write_output  <= '0';
           inc_waddr     <= '0';
           done          <= '0';

        when st1 =>

           if (term = '1') then
              next_state <= st5;
           else
             if (ready = '1') then
                next_state <= st2;
             else
                next_state <= st1;
             end if;
           end if;

           clear         <= '0';
           request       <= '0';
           init          <= '1';
           write_output  <= '0';
           inc_waddr     <= '0';
           done          <= '0';

        when st2 =>

           next_state <= st3;

           clear         <= '0';
           request       <= '1';
           init          <= '1';
           write_output  <= '1';
           inc_waddr     <= '0';
           done          <= '0';


        when st3 =>

           if (term = '1') then
              next_state <= st5;
           else
             if (ready = '1') then
                next_state <= st4;
             else
                next_state <= st3;
             end if;
           end if;

           clear         <= '0';
           request       <= '0';
           init          <= '0';
           write_output  <= '0';
           inc_waddr     <= to_mem;
           done          <= '0';

        when st4 =>

           next_state <= st3;

           clear         <= '0';
           request       <= '1';
           init          <= '0';
           write_output  <= '1';
           inc_waddr     <= '0';
           done          <= '0';
   
        when st5 =>

           next_state <= st0;

           clear         <= '0';
           request       <= '0';
           init          <= '0';
           write_output  <= '0';
           inc_waddr     <= '0';
           done          <= '1';
   
       end case;
    end if;
  end process state_comb;

end behavior;