library ieee;
use ieee.std_logic_1164.all;

entity fifo is
  generic (width: integer := 8;
           depth: integer := 4);
  port (data   : in  std_logic_vector(width-1 downto 0);
        q      : out std_logic_vector(width-1 downto 0);
        clk    : in  std_logic;
        reset  : in  std_logic;   -- Active high asynchronous clear
        re, we : in  std_logic;   -- Active high read/write enable
        ef, ff : buffer std_logic);  -- Active high empty/full flag
end fifo;

architecture behavior of fifo is

type MEM is array(0 to depth-1) of std_logic_vector(width-1 downto 0);
signal ramtmp: MEM;
signal waddr: integer;
signal raddr: integer;

begin

  -- #########################################################
  -- # Write Functional Section
  -- #########################################################
  write_pointer: process (reset, clk)
  begin
    if (reset = '1') then
      waddr <= 0;
    elsif (clk = '1' and clk'event) then
      if (we = '1') and (ff = '0') then
        if (waddr = depth-1) then
          waddr <= 0 after 2 ns;
        else
          waddr <= waddr+1 after 2 ns;
        end if;
      end if;
    end if; 
  end process;

  write_ram: process (clk)
  begin
    if (clk = '1' and clk'event) then
      if (reset = '0') and (ff = '0') then
        if (we = '1') then
          ramtmp(waddr) <= data after 1 ns;
        end if;
      end if;
    end if;
  end process;

  -- #########################################################
  -- # Read Functional Section
  -- #########################################################
  read_pointer: process (reset, clk)
  begin
    if (reset = '1') then
      raddr <= 0 after 1 ns;
    elsif (clk = '1' and clk'event) then
      if (re = '1') and (ef = '0') then
        if (raddr = depth-1) then
          raddr <= 0 after 2 ns;
        else
          raddr <= raddr+1 after 2 ns;
        end if;
      end if;
    end if; 
  end process;

  read_ram: process (clk)
  begin
    if (clk = '1' and clk'event) then
      if (reset = '0') and (ef = '0') then
        if (re = '1') then
          q <= ramtmp(raddr) after 1 ns;
        end if;
      end if;
    end if;
  end process;

  -- #########################################################
  -- # Full Flag Functional Section : Active high
  -- #########################################################
  ff_flag: process (reset, clk)
  begin
    if (reset = '1') then
      ff <= '0' after 1 ns;
    elsif (clk = '1' and clk'event) then
      if (we = '1' and re = '0') then
        if ((waddr = raddr-1) or ((waddr=depth-1) and (raddr=0))) then
          ff <= '1' after 5 ns;
        end if;
      elsif (we = '0' and re = '1') then
        ff <= '0' after 5 ns;
      end if;
    end if;     
  end process;

  -- #########################################################
  -- # Empty Flag Functional Section : Active high
  -- #########################################################
  ef_flag: process (reset, clk)
  begin
    if (reset = '1') then
      ef <= '1' after 1 ns;
    elsif (clk = '1' and clk'event) then
      if (we = '0' and re = '1') then
        if ((waddr = raddr+1) or ((raddr=depth-1) and (waddr=0))) then
          ef <= '1' after 5 ns;
        end if;
      elsif (we = '1' and re = '0') then
        ef <= '0' after 5 ns;
      end if;
    end if;     
  end process;

end behavior;