library ieee;
use ieee.std_logic_1164.all;
use work.all;
use work.parts.all;

entity cnt8 is
  port (clk, reset, ld, ce: in std_logic;
        d: in std_logic_vector (7 downto 0);
        q: out std_logic_vector (7 downto 0));
end;

architecture behavior of cnt8 is
begin
  u1: parts.countern generic map(8) 
      port map (clk=>clk, reset=>reset, ld=>ld, ce=>ce, d=>d, q=>q);
end behavior;