--
-- File:   ccmbasic.vhd
-- Author: CHEN, Qihong,  Portland State University
-- Date:   12/11/97
--

library ieee;
use ieee.std_logic_1164.all;
use work.ccmtype.all;

-------------------------------------------------------
-- Declare some complex components for CCM:
--   biu, ilu, ram, fifo
-------------------------------------------------------

package ccmbasic is

component biu
  port
   ( -- global signals and input data bus
     reset, clk : in std_logic;
     InstBus : in std_logic_vector (31 downto 23);
     DataBus : in std_logic_vector (8 downto 0);

     -- signals between CCM control unit and ILU
     loop_done, ilu_done, write_output2, inc_waddr2 : in std_logic;
     ilu_enable : buffer std_logic;
     to_mem : buffer std_logic;
     ilu_empty : in std_logic;

     -- signals between CCM control unit and the input/output Fifos
     infifoempty : in std_logic;
     read_fifo, write_fifo, finish: out std_logic;

     -- signals to Memory Address Units and Memory Banks
     ld_addrA, ld_addrB, ld_addrR : out std_logic;
     inc_addrA, inc_addrB : out std_logic;
     MemAwrite, MemAread : out std_logic;
     MemBwrite, MemBread : out std_logic;

     -- Load signals for registers
     ld_accu, ld_data, ld_water, ld_rightedge : out std_logic;
     ld_inst : buffer std_logic;
     ld_prpo : out std_logic; -- PreRelation and PreOperation

     -- Src signals
     CmpSrc, ASrc, OSrc: out std_logic;

     -- Control signals of Tri-state buffers
     EnAddrA, EnAddrB, EnIFifoA, EnIFifoD : buffer std_logic;
     MemARW, EnIluA, MemBRW, EnIluB       : buffer std_logic;

     -- current state of BIU-CU (just for debug)
     state : out BIUstate;

     -- signals for pre-relation and pre-operation
     prel_res : in std_logic;
     prel_sel : out std_logic_vector (1 downto 0)
   );
end component;

component ilu
  generic
   ( NumberOfIT : integer := 4 );  -- The number of ITs
  port
   ( reset, clk, ilu_enable, prime, to_mem, and_or : std_logic;
     rel, bef, act, aft: in std_logic_vector (0 to 3);
     water, redge: in std_logic_vector (0 to NumberOfIT - 1);
     a, b: in std_logic_vector (0 to (NumberOfIT * 2 - 1));
     c: out std_logic_vector (0 to (NumberOfIT * 2 - 1));
     ilu_done, write_output, inc_waddr, empty : out std_logic;
     cnt_val : out std_logic_vector(3 downto 0));
end component;

component ram
  generic
   ( Size     : integer := 64;    -- number of memory words
     AddrWidth: integer := 8;     -- number of address bits
     DataWidth: integer := 8;     -- number of bits per memory word
     download_on_power_up: boolean := true;
               -- if TRUE, RAM is downloaded at start of simulation
     download_filename: IN string := "ram_data.txt"
   );
  port
   ( ce : in std_logic;              -- Chip-Enable
     memread, memwrite: in std_logic;      -- read and write commands
     clk: in std_logic;              -- clock for write operation
     addr : in std_logic_vector (AddrWidth-1 downto 0);
     dbus : inout std_logic_vector (DataWidth-1 downto 0);
     dump : in std_logic;
        -- 0-to-1 transaction downloads the content of memory
        -- (dump_start to dump_end) to the log file
     dump_start: in integer;
     dump_end:   in integer
   );
end component;

component fifo 
  generic (width: integer := 8;
           depth: integer := 4);
  port (data   : in  std_logic_vector(width-1 downto 0);
        q      : out std_logic_vector(width-1 downto 0);
        clk    : in  std_logic;
        reset  : in  std_logic;   -- Active high asynchronous clear
        re, we : in  std_logic;   -- Active high read/write enable
        ef, ff : buffer std_logic);  -- Active high empty/full flag
end component;

end ccmbasic;