-- File:   ccm.vhd
-- Author: CHEN, Qihong,  Portland State University
-- Date:   3/30/97
--
-- Cube Calculus Machine Version 2 (CCM2 for short)
--
-- In this file, all components of CCM2 are combined together according
-- to figure 5.3 of the thesis. The reader should compare this code with
-- the figure 5.3 to understand it. 
--
-- Signals:
--   ififo_din: the input of the input FIFO.
--   ofifo_dout: the output of the output FIFO.
--   ififo_we: write enable signal of the input FIFO.
--   ififo_ff: full flag signal of the input FIFO.
--   ofifo_re: read enable signal of the output FIFO.
--   ofifo_ef: empty flag signal of the output FIFO.

library ieee;
use ieee.std_logic_1164.all;
use work.all;
use work.parts.all;
use work.ccmbasic.all;
use work.ccmtype.all;

entity ccm is
  port ( -- global signals
         reset, clk : in std_logic;

         -- the input/output FIFOs
         ififo_din : in std_logic_vector (31 downto 0); 
         ofifo_dout : out std_logic_vector (31 downto 0);
         ififo_we, ofifo_re : in std_logic;
         ififo_ff, ofifo_ef : buffer std_logic;

         -- current state of BIU (just for debug)
         state : out BIUstate
       );
end;

architecture arch of ccm is

  constant memSize : integer := 64;

  -- Bus signals
  signal IBus, OBus : std_logic_vector (31 downto 0);
  signal ABus : std_logic_vector (17 downto 0);
  signal DBusA, DBusB : std_logic_vector (29 downto 0);

  -- Tri-state buffer enable signals
  signal EnAddrA, EnAddrB, EnIFifoA, EnIFifoD : std_logic;
  signal MemARW, EnIluA, MemBRW, EnIluB       : std_logic;

  -- multiplexers select signals
  signal CmpSrc, ASrc, OSrc: std_logic;

  -- register/address unit load signals
  signal ld_accu, ld_data, ld_water, ld_rightedge, ld_inst : std_logic;
  signal ld_addrA, ld_addrB, ld_addrR : std_logic;

  -- memory address unit inc signals
  signal inc_addrA, inc_addrB : std_logic;

  -- memory read/write signals
  signal MemAwrite, MemAread, MemBwrite, MemBread : std_logic;

  -- signals related to the input/output Fifos
  signal ififo_ef, ofifo_ff, ififo_re, ofifo_we : std_logic;

  -- signals between BIU and ILU
  signal ilu_enable, ilu_done, write_output2, inc_waddr2, to_mem: std_logic;
  signal ilu_empty : std_logic;
  signal cnt_val : std_logic_vector(3 downto 0);
  signal cmp_q : std_logic_vector(0 to 3);

  -- enent flag signal
  signal addrEQ, finish : std_logic;

  -- pre-relation and pre-operation
  signal ld_prpo : std_logic;
  signal prpo_q : std_logic_vector (23 downto 0);
  signal rel, bef, tmp_and_or : std_logic_vector (0 to 3);
  signal and_or, prel_res : std_logic;
  signal prel_sel: std_logic_vector (1 downto 0);
  signal fourzero: std_logic_vector (0 to 3) := "0000";
  signal prel_val : std_logic_vector (3 downto 0);
  signal res_sel : std_logic_vector (1 downto 0);

  -- others
  signal const_one  : std_logic := '1';
  signal const_zero : std_logic := '0';
  signal addrA_q, addrB_q, addrR_q, CmpMux_q : std_logic_vector(17 downto 0);

  signal memaBus, membBus : std_logic_vector (31 downto 0);
  signal memaDump, membDump : std_logic := '0';
  signal a_dump_start, b_dump_start : integer := 0;
  signal a_dump_end, b_dump_end : integer := memSize;
  signal MemARWn, MemBRWn : std_logic;
  signal OMux_q, AMux_q : std_logic_vector (29 downto 0);

  signal accu_q, data_q : std_logic_vector (29 downto 0);
  signal water_q, right_q : std_logic_vector (14 downto 0);
  signal inst_q : std_logic_vector (17 downto 0);

  signal addra_clk, addrb_clk : std_logic;

begin

  biu: ccmbasic.biu port map
   ( reset=>reset, clk=>clk, 
     InstBus=>IBus(31 downto 23), DataBus=>IBus(8 downto 0),
     loop_done=>AddrEQ, ilu_done=>ilu_done, write_output2=>write_output2,
     inc_waddr2=>inc_waddr2, ilu_enable=>ilu_enable, to_mem=>to_mem,
     infifoempty=>ififo_ef, read_fifo=>ififo_re, 
     write_fifo=>ofifo_we,  finish=>finish,
     ld_addrA=>ld_addrA, ld_addrB=>ld_addrB, ld_addrR=>ld_addrR, 
     inc_addrA=>inc_addrA, inc_addrB=>inc_addrB,
     MemAwrite=>MemAwrite, MemAread=>MemAread,
     MemBwrite=>MemBwrite, MemBread=>MemBread,
     ld_accu=>ld_accu, ld_data=>ld_data, ld_water=>ld_water,
     ld_rightedge=>ld_rightedge, ld_inst=>ld_inst,
     CmpSrc=>CmpSrc, ASrc=>ASrc, OSrc=>OSrc,
     EnAddrA=>EnAddrA, EnAddrB=>EnAddrB, EnIFifoA=>EnIFifoA, 
     EnIFifoD=>EnIFifoD, MemARW=>MemARW, EnIluA=>EnIluA, 
     MemBRW=>MemBRW, EnIluB=>EnIluB, state=>state, ilu_empty=>ilu_empty,
     ld_prpo=>ld_prpo, prel_res=>prel_res, prel_sel=>prel_sel
   );

  tbuf_ibus_A : parts.tbufN generic map (18) port map
   ( en=>EnIFifoA, din=>IBus(17 downto 0), dout=>ABus );

  addra_clk <= inc_addrA or ld_AddrA;
  addrA: parts.counterN generic map (18) port map
   ( reset=>reset, clk=>addra_clk, ld=>ld_addrA, ce=>const_one, 
     d=>ABus, q=>addrA_q );

  tbuf_addrA: parts.tbufN generic map (18) port map
   ( en=>EnAddrA, din=>addrA_q, dout=>ABus );

  addrb_clk <= inc_addrB or ld_AddrB;
  addrB: parts.counterN generic map (18) port map
   ( reset=>reset, clk=>addrb_clk, ld=>ld_addrB, ce=>const_one,
     d=>ABus, q=>addrB_q );

  tbuf_addrB: parts.tbufN generic map (18) port map
   ( en=>EnAddrB, din=>addrB_q, dout=>ABus );

  addrR: parts.regN generic map (18) port map
   ( reset=>reset, load=>ld_addrR, d=>ABus, q=>addrR_q );

  mux_cmp: parts.mux21N generic map (18) port map
   ( din0=>addrA_q, din1=>addrB_q, sel=>CmpSrc, dout=>CmpMux_q );
 
  equ: parts.equalN generic map (18) port map
   ( din0=>CmpMux_q, din1=>addrR_q, o=>addrEQ );

  mema: ccmbasic.ram 
    generic map
     ( Size=>memSize, AddrWidth=>18, DataWidth=>32, download_on_power_up=>false)
    port map
     ( ce=>const_one, memread=>MemAread, memwrite=>MemAwrite,
       clk=>clk, addr=>addrA_q, dbus=>memaBus, dump=>memaDump,
       dump_start=>a_dump_start, dump_end=>a_dump_end
     );

  memb: ccmbasic.ram 
    generic map
     ( Size=>memSize, AddrWidth=>18, DataWidth=>32, download_on_power_up=>false)
    port map
     ( ce=>const_one, memread=>MemBread, memwrite=>MemBwrite,
       clk=>clk, addr=>addrB_q, dbus=>membBus, dump=>membDump,
       dump_start=>b_dump_start, dump_end=>b_dump_end
     );

  tbuf_mema_r: parts.tbufN generic map (30) port map
   ( en=>MemARW, din=>memaBus(29 downto 0), dout=>DBusA );

  tbuf_mema_w: parts.tbufN generic map (30) port map
   ( en=>MemARWn, din=>DBusA, dout=>memaBus(29 downto 0) );
  MemARWn <= not MemARW after 1 ns;

  tbuf_memb_r: parts.tbufN generic map (30) port map
   ( en=>MemBRW, din=>membBus(29 downto 0), dout=>DBusB );

  tbuf_memb_w: parts.tbufN generic map (30) port map
   ( en=>MemBRWn, din=>DBusB, dout=>membBus(29 downto 0) );
  MemBRWn <= not MemBRW after 1 ns;

  tbuf_ibus_D : parts.tbufN generic map (30) port map
   ( en=>EnIFifoD, din=>IBus(29 downto 0), dout=>DBusA );

  mux_o: parts.mux21N generic map (30) port map
   ( din0=>DBusA, din1=>DBusB, sel=>OSrc, dout=>OMux_q );

  mux_a: parts.mux21N generic map (30) port map
   ( din0=>DBusA, din1=>DBusB, sel=>ASrc, dout=>AMux_q );

  reg_accu: parts.regN generic map (30) port map
   ( reset=>reset, load=>ld_accu, d=>AMux_q, q=>accu_q );

  reg_data: parts.regN generic map (30) port map
   ( reset=>reset, load=>ld_data, d=>OMux_q, q=>data_q );

  reg_water: parts.regN generic map (15) port map
   ( reset=>reset, load=>ld_water, d=>OMux_q(14 downto 0), q=>water_q );

  reg_rightedge: parts.regN generic map (15) port map
   ( reset=>reset, load=>ld_rightedge, d=>OMux_q(14 downto 0), q=>right_q );

  reg_inst: parts.regN generic map (18) port map
   ( reset=>reset, load=>ld_inst, d=>OMux_q(17 downto 0), q=>inst_q );
  
  reg_prpo: parts.regN generic map (24) port map
   ( reset=>reset, load=>ld_prpo, d=>OMux_q(23 downto 0), q=>prpo_q );
  
  mux_rel: parts.mux441 port map
   ( din0=>prpo_q(22 downto 19), din1=>prpo_q(10 downto 7), 
     din2=>inst_q(15 downto 12), din3=>fourzero, 
     sel=>prel_sel, dout=>rel  );

  mux_bef: parts.mux441 port map
   ( din0=>prpo_q(15 downto 12), din1=>prpo_q(3 downto 0), 
     din2=>inst_q(11 downto 8), din3=>fourzero, 
     sel=>prel_sel, dout=>bef  );

  tmp_and_or <= prpo_q(23) & prpo_q(11) & inst_q(16) & const_zero;

  mux_and_or:parts.mux41 port map 
   ( din=>tmp_and_or, sel=>prel_sel, dout=>and_or);

  ilu: ccmbasic.ilu generic map (15) port map
   ( reset=>reset, clk=>clk, ilu_enable=>ilu_enable,
     prime=>inst_q(17), to_mem=>to_mem, and_or=>and_or,
     rel=>rel, bef=>bef,
     act=>inst_q(7 downto 4), aft=>inst_q(3 downto 0),
     water=>water_q, redge=>right_q, a=>accu_q, b=>data_q,
     c=>OBus(29 downto 0), ilu_done=>ilu_done,
     write_output=>write_output2, inc_waddr=>inc_waddr2, empty=>ilu_empty,
     cnt_val=>cnt_val
   );

  mux_pval: parts.mux21N generic map (size=>1) port map
   ( din0=>prpo_q(16 downto 16), din1=>prpo_q(4 downto 4),
     sel=>prel_sel(0), dout=>prel_val(0 downto 0));

  prel_val(3 downto 1) <= "000";

  cmp_prel: parts.cmpN generic map (size=>4) port map
   ( dinA=>cnt_val, dinB=>prel_val,
     lt=>cmp_q(0), eq=>cmp_q(1), gt=>cmp_q(2));

  cmp_q(3) <= '0';

  mux_res_sel: parts.mux21N generic map (size=>2) port map
   ( din0=>prpo_q(18 downto 17), din1=>prpo_q(6 downto 5),
     sel=>prel_sel(0), dout=>res_sel);

  mux_prel_res: parts.mux41 port map
   ( din=>cmp_q, sel=>res_sel, dout=>prel_res);

  tbuf_IluA: parts.tbufN generic map (30) port map
   ( en=>EnIluA, din=>OBus(29 downto 0), dout=>DBusA );

  tbuf_IluB: parts.tbufN generic map (30) port map
   ( en=>EnIluB, din=>OBus(29 downto 0), dout=>DBusB );

  ififo: ccmbasic.fifo 
    generic map (Width=>32, depth=>512)
    port map
     ( data=>ififo_din, q=>IBus, clk=>clk, reset=>reset,
       re=>ififo_re, we=>ififo_we, ef=>ififo_ef, ff=>ififo_ff 
     );

  ofifo: ccmbasic.fifo 
    generic map (Width=>32, depth=>64)
    port map
     ( data=>OBus, q=>ofifo_dout, clk=>clk, reset=>reset,
       re=>ofifo_re, we=>ofifo_we, ef=>ofifo_ef, ff=>ofifo_ff 
     );

  OBus(30) <= const_zero;
  OBus(31) <= finish;

end arch;