-- File:   biu_cu.vhd  
-- Author: CHEN, Qihong,  Portland State University
-- Date:   3/30/97
--
-- The control unit of GCU (it was called BIU, Bus Interface Unit)
--
-- Signals:
--   reset: global reset. this signal can be seen as chip reset.
--   clk: global clock signal.
--   infifoempty: whether the input FIFO is empty or not.
--   ilu_enable: ilu_enable signal.
--   ilu_done: ilu_done signal.
--   seq_com: sequential or combinational operation.
--   loop_done: whether a loop operation is done or not.
--   to_mem: toMem signal, one bit of config register.
--   opc: the highest 3 bits of CCM instructions, it's the op-code.
--   read_fifo: read the CCM instructions from the input FIFO.
--   write_fifo: write the result to the output FIFO.
--   ld_tbufs: load tri-state buffers control bits.
--   ld_regs: load registers.
--   ld_accu: load accumulator.
--   ld_data: load data register.
--   inc_raddr1: increase the source mem (for reading operands) address by 1 
--   inc_waddr1: increase the target mem (for writing results) address by 1.
--   finish: finish bit, see section 5.3.4 of the thesis.
--   write_output1: this signal is generated when there is a resultant cube.
--   mem_read: mem read signal, it is a temporary signal, see biu.vhd.
--   prel1,prel2,prel_res,prel_sel: see pre-relation/per-operation section in 
--                                  the thesis.
--
--  The section 5.4 of the thesis give a brief introduction to this finite
--  state machine. The GCU is used to deal with combinational cube operation
--  and pre-relation/pre-operation.

library ieee;
use ieee.std_logic_1164.all;
-- use work.parts;
use work.ccmtype.all;

entity biu_cu is
  port (reset, clk, ilu_done, infifoempty : in std_logic;
        seq_com, loop_done, to_mem: in std_logic;
        opc : in std_logic_vector (0 to 2);
        read_fifo, ilu_enable : out std_logic;
        ld_tbufs, ld_regs, ld_accu, ld_data : out std_logic;
        inc_raddr1, inc_waddr1, finish: out std_logic;
        write_fifo, write_output1, mem_read : out std_logic;
        state : out BIUstate;
        prel1, prel2, prel_res : in std_logic;
        prel_sel : out std_logic_vector(1 downto 0) );
end;

architecture behavior of biu_cu is
--  type BIUstate is (s0, s1, s2, s3, s4, s5, s6, s7, p1, ..., p7);
  signal present_state, next_state: BIUstate;
  signal cur_prel_sel, next_prel_sel: std_logic_vector(1 downto 0);

begin
 
  state <= present_state;
  prel_sel <= cur_prel_sel;
  
  state_clocked: process (clk) 
  begin
    if (clk'event and clk='1') then
       present_state <= next_state after 5 ns;
       cur_prel_sel <= next_prel_sel;
    end if;
  end process state_clocked;

  state_comb: process 
    ( present_state, reset, loop_done, infifoempty,
      to_mem, ilu_done, seq_com, opc(0), opc(1), opc(2),
      prel1, prel2, prel_res )
  begin

    if (reset = '1') then

       next_state <= s0;

    else

       case present_state is

         when s0 =>

           if (infifoempty = '1') then
              next_state <= s0;
           else
              next_state <= s1;
           end if;

           ilu_enable <= '0';
           ld_tbufs   <= '0';
           ld_regs    <= '0'; 
           ld_accu    <= '0';
           ld_data    <= '0';
           inc_raddr1 <= '0';
           inc_waddr1 <= '0';
           finish     <= '0';
           read_fifo  <= not infifoempty; 
           write_fifo <= '0';
           write_output1 <= '0';
           mem_read   <= '0';
           next_prel_sel   <= cur_prel_sel;

        when s1 =>

           if (opc(0) = '1') then
              if (opc(1) = '1') then
                 next_state <= s3;
              else
                 next_state <= s4;
              end if;
           else
              next_state <= s2;
           end if;

           ilu_enable <= '0';
           ld_tbufs   <= '0';
           ld_regs    <= '0'; 
           ld_accu    <= '0';
           ld_data    <= '0';
           inc_raddr1 <= '0';
           inc_waddr1 <= '0';
           finish     <= '0';
           read_fifo  <= '0';
           write_fifo <= '0';
           write_output1 <= '0';
           mem_read   <= '0';
           next_prel_sel   <= cur_prel_sel;

        when s2 =>

           next_state <= s0;

           ilu_enable <= '0';
           ld_tbufs   <= (not opc(0)) and (not opc(1)) and (not opc(2))
                         after 2 ns;
           ld_regs    <= (not opc(0)) and (not opc(1)) and opc(2)
                         after 2 ns;
           ld_accu    <= (not opc(0)) and opc(1)
                         after 2 ns;
           ld_data    <= '0';
           inc_raddr1 <= '0';
           inc_waddr1 <= '0';
           finish     <= '0';
           read_fifo  <= '0';
           write_fifo <= '0';
           write_output1 <= '0';
           mem_read   <= '0';
           next_prel_sel   <= cur_prel_sel;

        when s3 =>

           if (loop_done = '1') then
              next_state <= s0;
           else
              next_state <= s4;
           end if;

           ilu_enable <= '0';
           ld_tbufs   <= '0';
           ld_regs    <= '0'; 
           ld_accu    <= '0';
           ld_data    <= '0';
           inc_raddr1 <= '0';
           inc_waddr1 <= '0';
           finish     <= loop_done;
           read_fifo  <= '0';
           write_fifo <= loop_done;
           write_output1 <= '0';
           mem_read   <= '1';
           next_prel_sel <= cur_prel_sel;

        when s4 =>

           if (prel1 = '1') then
              next_state <= p2;
              next_prel_sel   <= "00";
           else
              next_state <= p1;
              next_prel_sel   <= "10";
           end if;

           ilu_enable <= '0';
           ld_tbufs   <= '0';
           ld_regs    <= '0'; 
           ld_accu    <= '0';
           ld_data    <= '1';
           inc_raddr1 <= '0';
           inc_waddr1 <= '0';
           finish     <= '0';
           read_fifo  <= '0';
           write_fifo <= '0';
           write_output1 <= '0';
           mem_read   <= '1';

        when p1 =>

           if (seq_com = '1') then
              next_state <= s5;
           else
              next_state <= s6;
           end if;

           ilu_enable <= '0';
           ld_tbufs   <= '0';
           ld_regs    <= '0'; 
           ld_accu    <= '0';
           ld_data    <= '0';
           inc_raddr1 <= '0';
           inc_waddr1 <= '0';
           finish     <= '0';
           read_fifo  <= '0';
           write_fifo <= '0';
           write_output1 <= '0';
           mem_read   <= '0';
           next_prel_sel <= cur_prel_sel;

        when s5 =>

           if (ilu_done = '1') then
              if opc(1) = '1' then
                 next_state <= s3;
              else
                 next_state <= s0;
              end if;
           else
              next_state <= s5;
           end if;

           ilu_enable <= not ilu_done;
           ld_tbufs   <= '0';
           ld_regs    <= '0'; 
           ld_accu    <= '0';
           ld_data    <= '0';
           inc_raddr1 <= ilu_done and opc(1);
           inc_waddr1 <= '0';
           finish     <= ilu_done and (not opc(1));
           read_fifo  <= '0';
           write_fifo <= ilu_done and (not opc(1));
           write_output1 <= '0';
           mem_read   <= '0';
           next_prel_sel <= cur_prel_sel;
   
        when s6 =>

           next_state <= s7;

           ilu_enable <= '0';
           ld_tbufs   <= '0';
           ld_regs    <= '0'; 
           ld_accu    <= '0';
           ld_data    <= '0';
           inc_raddr1 <= '0';
           inc_waddr1 <= '0';
           finish     <= '0';
           read_fifo  <= '0';
           write_fifo <= '0';
           write_output1 <= '1';
           mem_read   <= '0';
           next_prel_sel <= cur_prel_sel;
   
        when s7 =>

           if (opc(1) = '1') then
              next_state <= s3;
           else
              next_state <= s0;
           end if;

           ilu_enable <= '0';
           ld_tbufs   <= '0';
           ld_regs    <= '0'; 
           ld_accu    <= '0';
           ld_data    <= '0';
           inc_raddr1 <= opc(1);
           inc_waddr1 <= to_mem;
           finish     <= not opc(1);
           read_fifo  <= '0';
           write_fifo <= not opc(1);
           write_output1 <= '0';
           mem_read   <= '0';
           next_prel_sel <= cur_prel_sel;
   
        when p2 =>

           next_state <= p3;

           ilu_enable <= '0';
           ld_tbufs   <= '0';
           ld_regs    <= '0'; 
           ld_accu    <= '0';
           ld_data    <= '0';
           inc_raddr1 <= '0';
           inc_waddr1 <= '0';
           finish     <= '0';
           read_fifo  <= '0';
           write_fifo <= '0';
           write_output1 <= '0';
           mem_read   <= '0';
           next_prel_sel <= cur_prel_sel;

        when p3 =>

           if (prel_res = '1') then
              next_state <= p4;
              next_prel_sel <= cur_prel_sel;
           else
              if (prel2 = '1') then
                 next_state <= p5;
                 next_prel_sel <= "01";
              else
                 next_state <= p1;
                 next_prel_sel <= "10";
              end if;
           end if;

           ilu_enable <= '0';
           ld_tbufs   <= '0';
           ld_regs    <= '0'; 
           ld_accu    <= '0';
           ld_data    <= '0';
           inc_raddr1 <= '0';
           inc_waddr1 <= '0';
           finish     <= '0';
           read_fifo  <= '0';
           write_fifo <= '0';
           write_output1 <= '0';
           mem_read   <= '0';

        when p4 =>

           next_state <= s7;

           ilu_enable <= '0';
           ld_tbufs   <= '0';
           ld_regs    <= '0'; 
           ld_accu    <= '0';
           ld_data    <= '0';
           inc_raddr1 <= '0';
           inc_waddr1 <= '0';
           finish     <= '0';
           read_fifo  <= '0';
           write_fifo <= '0';
           write_output1 <= '1';
           mem_read   <= '0';
           next_prel_sel <= cur_prel_sel;

        when p5 =>

           next_state <= p6;

           ilu_enable <= '0';
           ld_tbufs   <= '0';
           ld_regs    <= '0'; 
           ld_accu    <= '0';
           ld_data    <= '0';
           inc_raddr1 <= '0';
           inc_waddr1 <= '0';
           finish     <= '0';
           read_fifo  <= '0';
           write_fifo <= '0';
           write_output1 <= '0';
           mem_read   <= '0';
           next_prel_sel <= cur_prel_sel;

        when p6 =>

           if (prel_res = '1') then
              next_state <= p7;
              next_prel_sel <= cur_prel_sel;
           else
              next_state <= p1;
              next_prel_sel <= "10";
           end if;

           ilu_enable <= '0';
           ld_tbufs   <= '0';
           ld_regs    <= '0'; 
           ld_accu    <= '0';
           ld_data    <= '0';
           inc_raddr1 <= '0';
           inc_waddr1 <= '0';
           finish     <= '0';
           read_fifo  <= '0';
           write_fifo <= '0';
           write_output1 <= '0';
           mem_read   <= '0';

        when p7 =>

           next_state <= s7;

           ilu_enable <= '0';
           ld_tbufs   <= '0';
           ld_regs    <= '0'; 
           ld_accu    <= '0';
           ld_data    <= '0';
           inc_raddr1 <= '0';
           inc_waddr1 <= '0';
           finish     <= '0';
           read_fifo  <= '0';
           write_fifo <= '0';
           write_output1 <= '1';
           mem_read   <= '0';
           next_prel_sel <= cur_prel_sel;

       end case;
    end if;
  end process state_comb;

end behavior;