-- File:   biu.vhd
-- Author: CHEN, Qihong,  Portland State University
-- Date:   3/30/97
--
-- Global Control Unit (GCU for short, it was called BIU, Bus Interface Unit)

library ieee;
use ieee.std_logic_1164.all;
use work.parts.all;
use work.ccmtype.all;

entity biu is
  port 
   ( -- global signals and input data bus
     reset, clk : in std_logic;
     InstBus : in std_logic_vector (31 downto 23); 
     -- InstBus is IBus(31 downto 23) in the thesis.
     DataBus : in std_logic_vector (8 downto 0);
     -- DataBus is IBus(8 downto 0) in the thesis.

     -- signals between GCU and ILU
     loop_done, ilu_done, write_output2, inc_waddr2 : in std_logic;
     ilu_enable : buffer std_logic;
     to_mem : buffer std_logic;
     ilu_empty : in std_logic;

     -- signals between GCU and the input/output Fifos
     infifoempty : in std_logic;
     read_fifo, write_fifo, finish: out std_logic;

     -- signals to Memory Address Units and Memory Banks from GCU
     ld_addrA, ld_addrB, ld_addrR : out std_logic;
     inc_addrA, inc_addrB : out std_logic;
     MemAwrite, MemAread : out std_logic;
     MemBwrite, MemBread : out std_logic;

     -- Load signals for registers generated by GCU
     ld_accu, ld_data, ld_water, ld_rightedge : out std_logic;
     ld_inst : buffer std_logic;
     ld_prpo : out std_logic; -- PreRelation and PreOperation

     -- multiplexers select signals (Src signals)
     CmpSrc, ASrc, OSrc: out std_logic;

     -- Control signals of Tri-state buffers 
     EnAddrA, EnAddrB, EnIFifoA, EnIFifoD : buffer std_logic;
     MemARW, EnIluA, MemBRW, EnIluB       : buffer std_logic;

     -- current state of BIU-CU (just for debug)
     state : out BIUstate;

     -- signals for pre-relation and pre-operation
     prel_res : in std_logic;
     prel_sel : out std_logic_vector (1 downto 0)
   );
end;

architecture arch of biu is

component biu_cu
  port (reset, clk, ilu_done, infifoempty : in std_logic;
        seq_com, loop_done, to_mem: in std_logic;
        opc : in std_logic_vector (0 to 2);
        read_fifo, ilu_enable : out std_logic;
        ld_tbufs, ld_regs, ld_accu, ld_data : out std_logic;
        inc_raddr1, inc_waddr1, finish: out std_logic;
        write_fifo, write_output1, mem_read : out std_logic;
        state : out BIUstate;
        prel1, prel2, prel_res : in std_logic;
        prel_sel : out std_logic_vector(1 downto 0) );
end component;

-- Sequential/combinational operation
signal seq_com : std_logic;

-- Output control bits
signal to_ofifo, to_accu : std_logic;

-- Load signals
signal ld_tbufs, ld_regs : std_logic;
signal ld_conf, ld_accu1, ld_accu2 : std_logic;

-- Output signals for conf_reg and 3-to-8 decoders
signal conf_reg : std_logic_vector (8 downto 0);
signal decoder_out : std_logic_vector (7 downto 0);

-- Tri-state buffers control bits and Buses status bits
signal ld_EnAddrA, ld_EnAddrB, ld_EnIFifoA, ld_EnIFifoD : std_logic;
signal ld_MemARW, ld_EnIluA, ld_MemBRW, ld_EnIluB : std_logic;

-- tempory tri-state control signals
signal  tEnAddrA, tEnAddrB, tEnIFifoA, tEnIFifoD : std_logic;
signal  tMemARW, tEnIluA, tMemBRW, tEnIluB       : std_logic;

-- Status of the 3 Buses
signal ABusStatus, DBusAStatus, DBusBStatus: std_logic;

-- Singals for Address Units 
signal inc_raddr, inc_waddr, inc_waddr1 : std_logic;

-- Signals for memory and outputs
signal mem_read, write_output, write_output1, write_fifo1 : std_logic;

-- Config bits
signal enMemA, enMemB, enFinish : std_logic;

-- temp signal
signal t_ilu_enable : std_logic;

-- pre-relation flags
signal prel1, prel2 : std_logic;

begin

  prel1_dff: dff port map 
   ( d=>InstBus(25), clk=>ld_inst, reset=>reset, q=>prel1);

  prel2_dff: dff port map 
   ( d=>InstBus(24), clk=>ld_inst, reset=>reset, q=>prel2);

  seq_com_dff: dff port map 
   ( d=>InstBus(23), clk=>ld_inst, reset=>reset, q=>seq_com);

  cu: biu_cu port map
   ( reset=>reset, clk=>clk, ilu_done=>ilu_done, infifoempty=>infifoempty,
     seq_com=>seq_com, loop_done=>loop_done, to_mem=>to_mem,
     opc=>InstBus(31 downto 29),
     read_fifo=>read_fifo, ilu_enable=>t_ilu_enable,
     ld_tbufs=>ld_tbufs, ld_regs=>ld_regs, 
     ld_accu=>ld_accu1, ld_data=>ld_data,
     inc_raddr1=>inc_raddr, inc_waddr1=>inc_waddr1, finish=>finish,
     write_fifo=>write_fifo1, write_output1=>write_output1, 
     mem_read=>mem_read, state=>state,
     prel1=>prel1, prel2=>prel2, prel_res=>prel_res, prel_sel=>prel_sel);

  ilu_enable <= t_ilu_enable;

  ----------------------------------------------------------------
  -- Address pointer
  ----------------------------------------------------------------

  -- Both BIU_CU and ILU_CU are able to generate inc_waddr (call inc_waddr1
  -- and inc_waddr2 here), the inc_waddr signal is finally generated here. 
  inc_waddr <= (inc_waddr1 or (ilu_enable and inc_waddr2)) and (not ilu_empty);

  -- inc_addrA is used to increase the address of mem bank A by 1
  inc_addrA <= enMemA and
               ((MemARW and inc_raddr) or ((not MemARW) and inc_waddr));

  -- inc_addrB is used to increase the address of mem bank B by 1
  inc_addrB <= enMemB and 
               ((MemBRW and inc_raddr) or ((not MemBRW) and inc_waddr));

  ----------------------------------------------------------------
  -- Load signals for output devices (mem, ofifo, accumulator)
  ----------------------------------------------------------------
 
  -- Both BIU_CU and ILU_CU are able to generate write_output (call 
  -- write_output1 and write_output2 here), the write_output signal
  -- is finally generated here. 
  write_output <= write_output1 or (ilu_enable and write_output2);

  -- write_fifo is used to write resultant cube to the output FIFO.
  write_fifo <= (write_output and to_oFifo and (not ilu_empty)) 
                or (write_fifo1 and enFinish);

  -- ld_accu1 is used to load operand cube into accumulator
  -- ld_accu2 is used to load resultant cube back to accumulator
  -- ld_accu combines ld_accu1 and ld_accu2 together.
  ld_accu2   <= write_output and to_accu;
  ld_accu    <= ld_accu1 or ld_accu2;
  
  -- MemAwrite is used to write resultant cube to the mem bank A.
  MemAwrite <= write_output and to_mem and (not MemARW) and enMemA
               and (not ilu_empty) after 3 ns;

  -- MemBwrite is used to write resultant cube to the mem bank B.
  MemBwrite <= write_output and to_mem and (not MemBRW) and enMemB
               and (not ilu_empty)  after 3 ns;

  ----------------------------------------------------------------
  -- Memory read signals
  ----------------------------------------------------------------
 
  -- MemAread is used to read operand cube from the mem bank A.
  MemAread <= mem_read and MemARW and enMemA after 3 ns;

  -- MemBread is used to read operand cube from the mem bank B.
  MemBread <= mem_read and MemBRW and enMemB after 3 ns;

  ----------------------------------------------------------------
  -- Config-register is used to store 8 config bits:
  -- enMemA, enMemB, CmpSrc, ASrc, OSrc, to_oFifo, to_accu, to_mem
  ----------------------------------------------------------------

  config_reg: regN generic map (Size=>9)  port map
   ( d=>DataBus(8 downto 0), load=>ld_conf, reset=>reset, q=>conf_reg);
  
  enFinish <= conf_reg(8);
  enMemA   <= conf_reg(7);
  enMemB   <= conf_reg(6);
  CmpSrc   <= conf_reg(5);
  ASrc     <= conf_reg(4);
  OSrc     <= conf_reg(3);
  to_oFifo <= conf_reg(2);
  to_accu  <= conf_reg(1);
  to_mem   <= conf_reg(0);

  decoder: decoder3to8 port map
   ( din=>InstBus(28 downto 26), dout=> decoder_out);

  ld_addrA     <= ld_regs and decoder_out(0);
  ld_addrB     <= ld_regs and decoder_out(1);
  ld_addrR     <= ld_regs and decoder_out(2);
  ld_water     <= ld_regs and decoder_out(3);
  ld_rightedge <= ld_regs and decoder_out(4);
  ld_inst      <= ld_regs and decoder_out(5);
  ld_conf      <= ld_regs and decoder_out(6);
  ld_prpo      <= ld_regs and decoder_out(7);
        
  ----------------------------------------------------------------
  -- tri-buffers connected to ABus
  ----------------------------------------------------------------

  -- Avoiding contention on ABus which would result from multiple
  -- drivers, see section 5.3.2 of the thesis.

  EnAddrA_dff: dff port map 
   ( d=>InstBus(25), clk=>ld_EnAddrA, reset=>reset, q=>tEnAddrA);
  EnAddrA <= tEnAddrA;

  EnAddrB_dff: dff port map 
   ( d=>InstBus(25), clk=>ld_EnAddrB, reset=>reset, q=>tEnAddrB);
  EnAddrB <= tEnAddrB;

  EnIFifoA_dff: dff port map 
   ( d=>InstBus(25), clk=>ld_EnIFifoA, reset=>reset, q=>tEnIFifoA);
  EnIFifoA <= tEnIFifoA;

  ABusStatus  <= not ((tEnAddrA or tEnAddrB or tEnIFifoA) and InstBus(25));
  ld_EnAddrA  <= decoder_out(0) and ABusStatus and ld_tbufs after 3 ns;
  ld_EnAddrB  <= decoder_out(1) and ABusStatus and ld_tbufs after 3 ns;
  ld_EnIFifoA <= decoder_out(2) and ABusStatus and ld_tbufs after 3 ns;

  ----------------------------------------------------------------
  -- tri-buffers connected to DBusA
  ----------------------------------------------------------------

  -- Avoiding contention on DBusA which would result from multiple
  -- drivers, see section 5.3.2 of the thesis.

  MemARW_dff: dff port map 
   ( d=>InstBus(25), clk=>ld_MemARW, reset=>reset, q=>tMemARW);
  MemARW <= tMemARW;

  EnIluA_dff: dff port map 
   ( d=>InstBus(25), clk=>ld_EnIluA, reset=>reset, q=>tEnIluA);
  EnIluA <= tEnIluA;

  EnIFifoD_dff: dff port map 
   ( d=>InstBus(25), clk=>ld_EnIFifoD, reset=>reset, q=>tEnIFifoD);
  EnIFifoD <= tEnIFifoD;

  DBusAStatus <= not ((tMemARW or tEnIluA or tEnIFifoD) and InstBus(25));
  ld_MemARW   <= decoder_out(3) and DBusAStatus and ld_tbufs after 3 ns;
  ld_EnIluA   <= decoder_out(4) and DBusAStatus and ld_tbufs after 3 ns;
  ld_EnIFifoD <= decoder_out(5) and DBusAStatus and ld_tbufs after 3 ns;

  ----------------------------------------------------------------
  -- tri-buffers connected to DBusB
  ----------------------------------------------------------------

  -- Avoiding contention on DBusB which would result from multiple
  -- drivers, see section 5.3.2 of the thesis.

  MemBRW_dff: dff port map 
   ( d=>InstBus(25), clk=>ld_MemBRW, reset=>reset, q=>tMemBRW);
  MemBRW <= tMemBRW;

  EnIluB_dff: dff port map 
   ( d=>InstBus(25), clk=>ld_EnIluB, reset=>reset, q=>tEnIluB);
  EnIluB <= tEnIluB;

  DBusBStatus <= not ((tMemBRW or tEnIluB) and InstBus(25));
  ld_MemBRW   <= decoder_out(6) and DBusBStatus and ld_tbufs after 3 ns;
  ld_EnIluB   <= decoder_out(7) and DBusBStatus and ld_tbufs after 3 ns;

end arch;