ECE 510 VHDL project #1

Submitted by Mani Sudha Yalamanchi (prasad@ece.pdx.edu)

Features

1. Sorts unsigned numbers in an ascending order (smallest number is
on the lower end).

2. Numbers are stored in a FIFO, i.e the first number in is the first
number to be replaced when a new number has to be put in.

3. Designed using generics.

a. w - bit width of numbers to be compared.

b. n - number of entries in FIFO.

Note: w and n should be at least 2.

Code

1. Click here for the sorter code.

2. Click here for the test bench.

Logic Design

Entity

The sorter is a sequential circuit. It has clock and reset pins.
It has a data valid strobe and an input data bus. The output is a
bus that consists of all the previous 'n' numbers sorted and appended together.
I would have preferred to have a separate data bus for each number, but
because I used Generics, there was no easy way to generate a 'generic specified'
number of output ports. On the other hand, I could use generics to
modify the width of the output port.

Every time a new number is specified (by asserting the 'valid' signal and putting the corresponding data on the 'data' bus), it is sorted with respect to the current state. The oldest number is removed. The sorted state is available in the next cycle as output.

Algorithm and Architecture

I looked at different traditional algorithms for sorting, bubble sort,
quick sort, insertion sort and so on. All the textbooks solved sorting
from a sequential processor point of view. In VHDL, statements can
be executed concurrently. Thus, it seemed that insertion sort is
most appropriate as comparisons can be made concurrently instead of in
an iterative loop. The basic idea as described in the book "How to Solve
it by Computer" is that sorting is done in the same way as we sort a 'hand'
of cards.

First, we pick a number(card) to replace, depending on its age. A counter (one hot encoded in this implementation) is used to keep track of the age of each number. The counters need to be initialized properly.

Next, we compare all the previous numbers with the current inputs. This gives us a vector (called comp_vector in the implementation). An edge in this vector indicates the location for the insertion of the new number (card). There are two positions on the edge where the number can be inserted, the high side or the low side. The high side is selected if the replacement position is to the left of the insertion position. The low side is selected if the replacement position is to the right of the insertion position.

Once the insertion and replacements locations have been selected, everything in between these pointers needs to be shifted right (if insertion pointer is less than replacement pointer) or left (if insertion pointer is less than the replacement pointer). Note that the counters indicating the age of the numbers will be incremented and shifted along with the numbers.

An example is given below.

If the current state is 89 32 6 2

with 89 at position 3, 32 at position 2, 6 at position 1 and 2 at position
0

and the ages of the numbers are 4 2 3 1.

A new number 16 has been input.

The number 89 needs to be replaced because it has the oldest age of
4. So the replacement vector is

1 0 0 0

The comparison vector (using old_number >= input data) would give

1 1 0 0.

The edge indicates that the new number will be in positions 1 or 2.
Since the replacement position is to the left, the high side, i.e. position
2 is selected for replacement.

Therefore the insertion vector is 0 1 0 0.

Now everything between positions 2 and 3 needs to be shifted right to fill the replacement position.

The output that is valid in the next cycle is

32 16 6 2

The corresponding ages of the numbers (after shifting and incrementing)
are

3 1 4 2

Test Bench

A test bench was written for the sorter. The test bench reuses
code from the test bench described in section 10.2.1 of the book "VHDL
for programmable logic"

The test bench creates many records for the inputs and the expected
outputs.

The output vector of the sorter is compared with the expected output
after every clock cycle.

Compilation

The vhdl code was compiled and simulated using Modelsim.

vlib work

vcom -93 -explicit sorter.vhd

vcom -93 -explicit sorter_tb.vhd

vsim sorter_tb

run 3000ns

Simulation

Only two configurations were tested. 4 entry 16-bit sorter and 8 entry
8-bit sorter. Simulations were run using modelsim. All the tests
passed.

Synthesis

I have tried to make the sorter synthesizable by using a RTL type of
coding methodology. I have not synthesized it though and have some questions
about the synthesis aspects of using generics.

References:

1. How to solve it by computer. R.G.Dromey. Prentice Hall

2. VHDL for programmable logic. Kevin Skahill. Addison Wessley