### LCM calculator ECE 510 VHDL project #2 Submitted by Mani Sudha Yalamanchi (prasad@ece.pdx.edu) Date: 05/07/2001

#### 1. Description

The objective of this project is to design a unit that calculates the LCM of two numbers.  The design should show a clear differentiation between datapath and control.  It should also be synthesizable.
The LCM calculator is a sequential circuit.  It takes 5 inputs, a clock (clk), a reset (reset), first number (a), second number (b) and an enable (en) signal that starts computation.
It has 3 outputs, the computed lcm number (lcm), a signal that is asserted when the computation is completed (done) and overflow signal that is asserted when the computed lcm can not be represented by the unit's vector width (overflow).\

### 2. Code

Radix2 divider (div.vhd)
LCM calculator (lcm.vhd)

#### 3. Algorithm

The algorithm consists of the following steps.
1. Pick the larger of the two numbers.
2. Then generate multiples of this number by using an Adder.
3. Every multiple is then divided by the smaller number to see if the remainder is zero.
4. If the remainder is zero, then the adder output is the LCM, assert DONE.
5. If the remainder is not zero, try again by generating a new multiple (i.e. by adding the number to the accumulated adder output).
6. If the LCM is not computed and the adder output overflows, assert DONE and signal an OVERFLOW exception.

#### 4. Logic Design

The block diagram for the LCM unit is given here.
##### 4.1 Datapath
The datapath consists of an adder, a divider, registers and muxes.  The adder is used to generate multiples.  The divider is used to check if the smaller number divides the multiples with a remainder of zero.  A register is used at the output of the adder to generate the next multiple.  Multiplexers are used to select the larger of the two input numbers to build the multiples and to select the smaller of the two numbers to use as the divisor for the DIVIDE unit.

The DIVIDE unit is code using Radix 2 restoring division algorithm described in Appendix 1 of the textbook "Computer Architecture: A Quantitative Approach" by Hennessy and Patterson.  The DIVIDE unit takes 'n' cycles where n is the width of the binary numbers, to calculate the remainder and quotient.

##### 4.2 Control logic
The control unit consists of the logic that synchronizes the "Muliple generating adder" and the DIVIDE unit.  It also generate the ouput signals that are asserted when the computation is done.

#### 5. Compilation

The logic is compiled and simulated using Modelsim.  The following commands were used.
\$>vlib work
\$>vcom -93 -explicit div.vhd
\$>vcom -93 -explicit lcm.vhd

#### 6. Simulation

The simulation was done using Modelsim and by applying patterns  to the input signals and observer the output waveforms.
A sample modelsim '.do' file used to test the DIVIDER unit is given here.
A sample modelsim.'.do' file used to test the LCM unit is given here.

#### 7. Synthesis

I have had tool problems and lack experience with Synthesis tools.  The code was written without using an behavioral contructs.  It is clearly divided into datapath and control. I do use some operators but I think synthesis tools support operators. I dont expect any problems with synthesis.  I will try it out later.

#### 8. References

1.Computer Architecture. A Quantitative Approach, John Hennessy and David Patterson, Morgan Kaufman Publishers,