--------------------------------------------------------
-- PSU510H Assignment 1
-- sorter.vhd
-- 8 entry 8-bit unsigned integer sorter
-- Authors: Ram Koganti (rkoganti@ichips.intel.com)
--          Khader Mohammad (rkoganti@ichips.intel.com)
---------------------------------------------------------

----------------------------------------
-- package declaration
--
----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package sorter_basic_pkg is 
	component agtb
		port ( DataIn, RegVal: in std_logic_vector(7 downto 0);
		       RegValGTDataIn: buffer std_logic);	
	end component;
	component rst_en_reg8 
		port( clk, reset, enable: in std_logic;
		      d: in std_logic_vector(7 downto 0);
		      q: buffer std_logic_vector(7 downto 0));
	end component;
	component inpmux
		port( 	D1, D2, D3: in std_logic_vector(7 downto 0);
			Cntrl: in std_logic_vector(1 downto 0);	
			Q: out std_logic_vector(7 downto 0));
	end component;
end sorter_basic_pkg;

-------------------------------------------
-- basic sorter block package declaration
--
-------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package sorter_block_pkg is
	component gensortreg
	  port(	clk, reset, enable: in std_logic;
		Shift, Load, Recycle: in std_logic_vector(7 downto 0);
		Bprev: in std_logic;
		Bnext: buffer std_logic;
		Dout: buffer std_logic_vector(7 downto 0));
	end component;
end sorter_block_pkg;


----------------------------------------
-- 8 bit register with reset and enable 
-- 
----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity rst_en_reg8 is
	port( clk, reset, enable: in std_logic;
	      d: in std_logic_vector(7 downto 0);
	      q: buffer std_logic_vector(7 downto 0));
end rst_en_reg8;

architecture dataflow of rst_en_reg8 is
begin
p1: process(reset, clk) begin
	if (reset = '1') then
		q <= (others => '0');
   	 elsif (clk'event and clk='1') then		
	        if enable = '1' then 
			q <= d;
		else 
			q <= q;
		end if;
	 end if;
   end process;				
end dataflow;

---------------------------------------
-- mux that loads/shifts/recycles
--
---------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity inpmux is	
	port( 	D1, D2, D3: in std_logic_vector(7 downto 0);
		Cntrl: in std_logic_vector(1 downto 0);	
		Q: out std_logic_vector(7 downto 0));
end inpmux;

architecture mux_behav of inpmux is
begin 
p1: process (cntrl) begin
	if Cntrl = "00" then 
		Q <= D1;
	end if;
        if Cntrl = "10" then 
		Q <= D2;
	end if;
        if Cntrl = "11" then 
		Q <= D3; 
	end if;
   end process;
end mux_behav;

-----------------------------------------
-- A > B comparator
--
-----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--use work.std_arith.all;
entity agtb is 
	port ( DataIn, RegVal: in std_logic_vector(7 downto 0);
	       RegValGTDataIn: buffer std_logic);
end agtb;

architecture agtb_arch of agtb is
begin
	RegValGTDataIn <= '1' when (RegVal > DataIn) else '0';

end agtb_arch;

-----------------------------------------------------
-- basic sorting block (generalized register)
--
-----------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.sorter_basic_pkg.all;
entity gensortreg is
	port(	clk, reset, enable: in std_logic;
		Shift, Load, Recycle: in std_logic_vector(7 downto 0);
		Bprev: in std_logic;
		Bnext: buffer std_logic;
		Dout: buffer std_logic_vector(7 downto 0));
end gensortreg;

architecture structural of gensortreg is 
signal Cntrl: std_logic_vector(1 downto 0);
signal A: std_logic;
signal muxout: std_logic_vector(7 downto 0);
begin
	-- instantiations	
	GTInst: agtb port map (Load, Dout, Bnext);
	RegInst: rst_en_reg8 port map (clk, reset, enable, muxout, Dout);
	MuxInst: inpmux port map (shift, load, recycle, Cntrl, muxout);

	-- concurrent statements

	A <= Bnext OR Bprev;	
	Cntrl <= (0=>Bnext, 1=>A);	
end structural;
					
----------------------------------------
-- 8 bit 8 entry sorter
--
----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.sorter_block_pkg.all;
entity sorter8x8 is
	port( 	clk, reset, enable: in std_logic;
		DataIn: in std_logic_vector(7 downto 0);
		Dout1, Dout2, Dout3, Dout4, Dout5, Dout6, Dout7, Dout8: 
				 buffer std_logic_vector (7 downto 0));	
end sorter8x8;

architecture sorter_structure of sorter8x8 is
signal Bnext1, Bnext2, Bnext3, Bnext4, Bnext5, Bnext6, Bnext7, Bnext8: 
			std_logic;
signal high_val: std_logic;
begin
	-- multiple instantiations of the generalized sorter register
	-- instantiations	
	Reg1: gensortreg port map (clk, reset, enable, DataIn, DataIn,
			Dout1, high_val, Bnext1, Dout1);
        Reg2: gensortreg port map (clk, reset, enable, Dout1, DataIn, 
			Dout2, Bnext1, Bnext2, Dout2);
        Reg3: gensortreg port map (clk, reset, enable, Dout2, DataIn, 
			Dout3, Bnext2, Bnext3, Dout3);
        Reg4: gensortreg port map (clk, reset, enable, Dout3, DataIn, 
			Dout4, Bnext3, Bnext4, Dout4);
        Reg5: gensortreg port map (clk, reset, enable, Dout4, DataIn, 
			Dout5, Bnext4, Bnext5, Dout5);
        Reg6: gensortreg port map (clk, reset, enable, Dout5, DataIn, 
			Dout6, Bnext5, Bnext6, Dout6);
        Reg7: gensortreg port map (clk, reset, enable, Dout6, DataIn, 
			Dout7, Bnext6, Bnext7, Dout7);
	Reg8: gensortreg port map (clk, reset, enable, Dout7, DataIn,
			DataIn, Bnext7, Bnext8, Dout8);
	high_val <= '1';
end sorter_structure;