-------------------------------------------------------- -- GCD circuit component package -- This file contains all the entities used by the GCD -- circuit. -- Authors: Ram Koganti and Khader Mohammad -- Date: 4/29/98 -------------------------------------------------------- package gcd_comp_pkg is component mux8_2 port( D0, D1: in bit_vector(7 downto 0); S: in bit; Dat: out bit_vector(7 downto 0)); end component; component AcomB port( A,B: in bit_vector(7 downto 0); AgtB: out bit; AeqB: out bit; AltB: out bit); end component; component AminusB port (A, B: in bit_vector(7 downto 0); AminusB: out bit_vector(7 downto 0)); end component; component rst_en_reg8 port( clk, reset, enable: in bit; d: in bit_vector(7 downto 0); q: buffer bit_vector(7 downto 0)); end component; component lfsr_8 generic (initval: bit_vector (7 downto 0) := "00000000"); port ( clk: in bit; randout: buffer bit_vector(7 downto 0) := initval); end component; end gcd_comp_pkg; --------------------------------------- -- 8-bit 1-select multiplexer -- This multiplexer is used to chose -- one of two 8-bit integers --------------------------------------- entity mux8_2 is port( D0, D1: in bit_vector(7 downto 0); S: in bit; Dat: out bit_vector(7 downto 0)); end mux8_2; architecture structural of mux8_2 is begin g1: FOR i IN 0 TO 7 GENERATE Dat(i) <= (D1(i) AND S) OR (D0(i) AND (NOT S)); END GENERATE; end structural; ---------------------------------------- -- AcomB comparator -- 8-bit A > B, A = B and A < B -- comparator implemented using -- standard gates ---------------------------------------- entity AcomB is port( A,B: in bit_vector(7 downto 0); AgtB: out bit; AeqB: out bit; AltB: out bit); end AcomB; architecture structural of AcomB is signal AxnorB: bit_vector(7 downto 0); begin AxnorB <= NOT (A xor B); AeqB <= AxnorB(0) AND AxnorB(1) AND AxnorB(2) AND AxnorB(3) AND AxnorB(4) AND AxnorB(5) AND AxnorB(6) AND AxnorB(7); AgtB <= (A(7) AND NOT B(7)) OR (AxnorB(7) AND A(6) AND NOT B(6)) OR (AxnorB(7) AND AxnorB(6) AND A(5) AND NOT B(5)) OR (AxnorB(7) AND AxnorB(6) AND AxnorB(5) AND A(4) AND NOT B(4)) OR (AxnorB(7) AND AxnorB(6) AND AxnorB(5) AND AxnorB(4) AND A(3) AND NOT B(3)) OR (AxnorB(7) AND AxnorB(6) AND AxnorB(5) AND AxnorB(4) AND AxnorB(3) AND A(2) AND NOT B(2)) OR (AxnorB(7) AND AxnorB(6) AND AxnorB(5) AND AxnorB(4) AND AxnorB(3) AND AxnorB(2) AND A(1) AND NOT B(1)) OR (AxnorB(7) AND AxnorB(6) AND AxnorB(5) AND AxnorB(4) AND AxnorB(3) AND AxnorB(2) AND AxnorB(1) AND A(0) AND NOT B(0)); AltB <= (B(7) AND NOT A(7)) OR (AxnorB(7) AND B(6) AND NOT A(6)) OR (AxnorB(7) AND AxnorB(6) AND B(5) AND NOT A(5)) OR (AxnorB(7) AND AxnorB(6) AND AxnorB(5) AND B(4) AND NOT A(4)) OR (AxnorB(7) AND AxnorB(6) AND AxnorB(5) AND AxnorB(4) AND B(3) AND NOT A(3)) OR (AxnorB(7) AND AxnorB(6) AND AxnorB(5) AND AxnorB(4) AND AxnorB(3) AND B(2) AND NOT A(2)) OR (AxnorB(7) AND AxnorB(6) AND AxnorB(5) AND AxnorB(4) AND AxnorB(3) AND AxnorB(2) AND B(1) AND NOT A(1)) OR (AxnorB(7) AND AxnorB(6) AND AxnorB(5) AND AxnorB(4) AND AxnorB(3) AND AxnorB(2) AND AxnorB(1) AND B(0) AND NOT A(0)); end structural; ---------------------------------------- -- 8-bit subtractor (A-B) -- uses a carry lookahead adder -- and 2's complement ---------------------------------------- entity AminusB is port ( A, B: in bit_vector(7 downto 0); AminusB: out bit_vector(7 downto 0)); end AminusB; architecture structural of AminusB is signal Bcompl, P, G, C: bit_vector(7 downto 0); begin Bcompl <= NOT B; P <= A XOR Bcompl; G <= A AND Bcompl; C(0) <= '1'; g1: FOR i IN 0 TO 7 GENERATE AminusB(i) <= P(i) XOR C(i); END GENERATE; C(1) <= G(0) OR (P(0)); C(2) <= G(1) OR (P(1) AND G(0)) OR (P(1) AND P(0)); C(3) <= G(2) OR (P(2) AND G(1)) OR (P(2) AND P(1) AND G(0)) OR (P(2) AND P(1) AND P(0)); C(4) <= G(3) OR (P(3) AND G(2)) OR (P(3) AND P(2) AND G(1)) OR (P(3) AND P(2) AND P(1) AND G(0)) OR (P(3) AND P(2) AND P(1) AND P(0)); C(5) <= G(4) OR (P(4) AND G(3)) OR (P(4) AND P(3) AND G(2)) OR (P(4) AND P(3) AND P(2) AND G(1)) OR (P(4) AND P(3) AND P(2) AND P(1) AND G(0)) OR (P(4) AND P(3) AND P(2) AND P(1) AND P(0)); C(6) <= G(5) OR (P(5) AND G(4)) OR (P(5) AND P(4) AND G(3)) OR (P(5) AND P(4) AND P(3) AND G(2)) OR (P(5) AND P(4) AND P(3) AND P(2) AND G(1)) OR (P(5) AND P(4) AND P(3) AND P(2) AND P(1) AND G(0)) OR (P(5) AND P(4) AND P(3) AND P(2) AND P(1) AND P(0)); C(7) <= G(6) OR (P(6) AND G(5)) OR (P(6) AND P(5) AND G(4)) OR (P(6) AND P(5) AND P(4) AND G(3)) OR (P(6) AND P(5) AND P(4) AND P(3) AND G(2)) OR (P(6) AND P(5) AND P(4) AND P(3) AND P(2) AND G(1)) OR (P(6) AND P(5) AND P(4) AND P(3) AND P(2) AND P(1) AND G(0)) OR (P(6) AND P(5) AND P(4) AND P(3) AND P(2) AND P(1) AND P(0)); end structural; ---------------------------------------- -- subtractor circuit optimized for area ---------------------------------------- architecture Area_Optimized of AminusB is signal Bcompl, P, G, C: bit_vector(7 downto 0); begin Bcompl <= NOT B; P <= A XOR Bcompl; G <= A AND Bcompl; C(0) <= '1'; g1: FOR i IN 0 TO 7 GENERATE AminusB(i) <= P(i) XOR C(i); END GENERATE; g2: FOR i IN 1 TO 7 GENERATE C(i) <= G(i-1) OR (P(i-1) AND C(i-1)); END GENERATE; end Area_Optimized; ---------------------------------------- -- reset and enable 8 bit register -- ---------------------------------------- entity rst_en_reg8 is port( clk, reset, enable: in bit; d: in bit_vector(7 downto 0); q: buffer bit_vector(7 downto 0)); end rst_en_reg8; architecture dataflow of rst_en_reg8 is begin p1: process(reset, clk) begin if (reset = '1') then q <= (others => '0'); elsif (clk'event and clk='1') then if enable = '1' then q <= d; else q <= q; end if; end if; end process; end dataflow; ------------------------------------------------ -- 8-bit linear feedback shift register -- used to generate inputs patterns in the -- test bench. ------------------------------------------------ entity lfsr_8 is generic (initval: bit_vector (7 downto 0) := "00000000"); port ( clk: in bit; randout: buffer bit_vector(7 downto 0) := initval); end lfsr_8; architecture dataflow of lfsr_8 is signal din: bit_vector (7 downto 0); begin p1: process(clk) begin if(clk'event AND clk='1') then randout <= din; end if; end process; din(0) <= NOT (NOT (NOT (randout(7) XOR randout(5)) XOR randout(4)) XOR randout(3)); g1: FOR i IN 1 TO 7 GENERATE din(i) <= randout(i-1); END GENERATE; end dataflow;