---------------------------------------------
-- GCD.VHD
-- entity computes the greates common
-- divider of two 8-bit integers.
-- Ram Koganti (rkoganti@ichips.intel.com)
-- Khader Mohammad (kmohamm@ichips.intel.com)
-- Date: 4/30/98
----------------------------------------------

package gcd_pkg is
	component gcd_comp
		port (	NUM1, NUM2: in bit_vector(7 downto 0);
			RESET, START, CLK: in bit;
			GCD: out bit_vector(7 downto 0);
			GCDValid: buffer bit);
	end component;
end gcd_pkg;


entity GCD_COMP is 
	port (	NUM1, NUM2: in bit_vector(7 downto 0);
		RESET, START, CLK: in bit;
		GCD: out bit_vector(7 downto 0);
		GCDValid: buffer bit);
end GCD_COMP;

use work.gcd_comp_pkg.all;
architecture structural of GCD_COMP is 
signal inpmux1_out, inpmux2_out, reg1, reg2: bit_vector(7 downto 0);
signal RegMuxIn1, RegMuxIn2: bit_vector(7 downto 0);
signal Reg1Input, Reg2Input: bit_vector(7 downto 0);
signal AgtB, aeqB, AltB: bit;
signal OutMuxSelect, Reg2GCD, Reg1GCD: bit;
signal enable, busy: bit;
begin

	-- instantiate registers
	
	Reg1Inst:  rst_en_reg8 port map (clk, reset, enable, Reg1Input, Reg1);
	Reg2Inst:  rst_en_reg8 port map (clk, reset, enable, Reg2Input, Reg2);
	
	-- instantiate muxes

	-- If the component is busy computing the GCD, this mux is used to 
	-- the registers.  If the component is not busy, then it is used to 
	-- load user input.
	--
	
	INPMUX1: mux8_2 port map (NUM1, reg1, BUSY, inpmux1_out);
	INPMUX2: mux8_2 port map (NUM2, reg2, BUSY, inpmux2_out);

	Reg2Mux: mux8_2 port map (RegMuxIn1, RegMuxIn2, AltB, Reg2Input);
	Reg1Mux: mux8_2 port map (inpmux2_out, inpmux1_out, AltB, Reg1Input);
		
	OutMux:  mux8_2 port map (Reg1, Reg2, OutMuxSelect, GCD);

	-- instantiate subtractors
	SUB12:  AminusB port map (inpmux1_out, inpmux2_out, RegMuxIn1);
	SUB21:	AminusB port map (inpmux2_out, inpmux1_out, RegMuxIn2);

	-- instantiate comparators
	GTComp: AcomB port map (inpmux1_out, inpmux2_out, AgtB, aeqB, AltB);

	-- control logic

	Reg2GCD <= NOT (Reg1(0) OR Reg1(1) OR Reg1(2) OR Reg1(3)  OR
		   Reg1(4) OR Reg1(5) OR Reg1(6) OR Reg1(7));
	Reg1GCD <= NOT (Reg2(0) OR Reg2(1) OR Reg2(2) OR Reg2(3)  OR
		   Reg2(4) OR Reg2(5) OR Reg2(6) OR Reg2(7));

	enable <= BUSY OR START;

	BUSY <= NOT GCDValid;

	GCDValid <= (Reg2GCD OR Reg1GCD);

	-- priority resolution in case both registers have a zero
	-- Reg1 get's priority

	OutMuxSelect <= Reg2GCD AND NOT Reg1GCD;

end structural;