---------------------------------------------------- -- PSU510VH Spring'98 Assignment 2 -- comptest.vhd -- Authors: Ram Koganti(rkoganti@ichips.intel.com) -- Khader Mohammad(kmohamm@ichips.intel.com) -- Date: 4/30/98 -- This file contains test benches used to test -- 1. GCD circuit -- 2. components used by the GCD circuit. ---------------------------------------------------- -------------------------------------------------- -- Test bench to test components used in the -- GCD circuit -- Components tested are -- AminusB (subtractor) -- AcomB (<,=,> comparator) -- Mux8_2 (8 bit, 1 select mux) -- TestBench uses a tabular approach to apply -- test patterns -------------------------------------------------- entity comptest is end comptest; use work.gcd_pkg.all; use work.gcd_comp_pkg.all; architecture behav_test of comptest is signal Ain, Bin: bit_vector(7 downto 0); signal S, clk: bit; signal AsubB, Dat: bit_vector(7 downto 0); signal AeqB, AgtB, AltB: bit; begin -- generate A, B and S using the lfsr A: lfsr_8 generic map (initval => "00101011") port map (clk => clk, randout => Ain); B: lfsr_8 generic map (initval => "10111110") port map (clk => clk, randout => Bin); S <= Ain(0) XOR Bin(0); -- gcd components instantiation Mux: mux8_2 port map (Ain, Bin, S, Dat); Comp: AcomB port map (Ain, Bin, AgtB, AeqB, AltB); Subt: AminusB port map (Ain, Bin, AsubB); -- generate clk CLOCK: process begin CLK <= '0', '1' after 50 ns; wait for 100 ns; end process; end behav_test; ----------------------------------------------------- -- test bench to check GCD design -- generates two pseduo-random numbers and -- computes the GCD for them. ----------------------------------------------------- entity gcdtest is end gcdtest; use work.gcd_pkg.all; use work.gcd_comp_pkg.all; architecture gcd_test of gcdtest is signal NUM1, NUM2: bit_vector(7 downto 0); signal reset, start, clk: bit; signal gcd: bit_vector(7 downto 0); signal gcdvalid: bit; signal input_clk: bit; begin -- gcd instantiation (unit under test) UUT: gcd_comp port map ( NUM1, NUM2, RESET, START, CLK, GCD, GCDValid); -- initialize LFRS's to generate test patterns. LFSR1: lfsr_8 generic map (initval => "11010011") port map (clk => input_clk, randout => NUM1); LFSR2: lfsr_8 generic map (initval => "10111101") port map (clk => input_clk, randout => NUM2); -- lfsr's are toggled only after GCD computation has been completed. -- input_clk <= clk AND gcdvalid; start <= gcdvalid; -- generate clk clk <= not(clk) after 50 ns; -- initialize by pulling reset reset <= '1','0' after 100 ns; end gcd_test; ----------------------------------- -- configurations necessary to -- simulate the test benches. ----------------------------------- configuration cfg_comptest of comptest is for behav_test for Subt: AminusB use entity work.AminusB(Area_Optimized); end for; end for; end; configuration cfg_gcdtest of gcdtest is for gcd_test end for; end;