//  6 bit up down counter with async reset.
//  Author:  Andrew Iverson
//  Date:  12-7-99
// 
//-----------------------------------------

module udcount(count_data, clk, up, down, n_reset);

  output [5:0] count_data;
  input clk, up, down, n_reset;

  reg [5:0] count_data;

  always @ (negedge clk or negedge n_reset)
  begin
    if (!n_reset)
      count_data <= 6'b0;
    else
    begin
      if (up)
        count_data <= count_data + 6'b000001;
      if (down)
        count_data <= count_data - 6'b000001;
    end
  end
endmodule