/* 16 deep x 12 wide synchronous RAM
* Steve Harwood, PSU EE572, Fall 1999
* 
* In this application, the bottom 8 addresses are loaded with 
* appropriate non-zero FIR filter tap values.  The top 8 addresses are loaded
* with zero for occasions where the data into the FIR is zero.
*/

module ram9x12(clk,we,addr,din,dout);
 input clk, we;
 input [3:0] addr;
 input [11:0] din;

 output [11:0] dout;
 
 reg [11:0] mem[15:0];
 wire [11:0] dout;

 always @(posedge clk)
  if (we) mem[addr] = din;

 assign dout = mem[addr];

endmodule