//  Parallel to serial shift register module.  8bits in, 1 bit out MSB first.
//  Negedge of s_clk && load causes new data to be loaded into the shift register.
//  Serial data is shifted out on the negedge of the s_clk, so the data is
//  valid on the posedge.  
//
//  Author:  Andrew Iverson
//  Date:  11-21-99
//  
//--------------------------------------------------------------------------

module p2s(s_data_out, n_reset, load, p_data_in, s_clk);

  output s_data_out;
  input [7:0] p_data_in;
  input load, s_clk, n_reset;

  reg [7:0] temp_p_data_in;

  assign s_data_out = temp_p_data_in[7];

  always @ (posedge s_clk or negedge n_reset)
  begin
    if (!n_reset)
    begin
      temp_p_data_in <= 8'b0;
    end
    else
    begin
      if (load)
	    temp_p_data_in <= p_data_in;
	  else
      begin	
        temp_p_data_in[7] <= temp_p_data_in[6];
        temp_p_data_in[6] <= temp_p_data_in[5];
        temp_p_data_in[5] <= temp_p_data_in[4];
        temp_p_data_in[4] <= temp_p_data_in[3];
        temp_p_data_in[3] <= temp_p_data_in[2];
        temp_p_data_in[2] <= temp_p_data_in[1];
        temp_p_data_in[1] <= temp_p_data_in[0];
        temp_p_data_in[0] <= 1'b0;
      end
    end
  end

endmodule