//  32 Byte Fifo ram block
//  Author:  Andrew Iverson
//  Date: 12-7-99
//  
//-------------------------

module fifo_ram(data_out, data_in, rd_addr, wr_addr, write_en, write_clk);

  output [7:0] data_out;
  input [7:0] data_in;
  input [4:0] rd_addr, wr_addr;
  input write_en, write_clk;

  reg [7:0] ram_block [31:0];
  

  assign data_out = ram_block[rd_addr];

  always @ (posedge write_clk)
  begin
    if (write_en)
      ram_block[wr_addr] <= data_in;
  end

endmodule