//  Clock MOD  module.  50Mhz in, 5.152 out, 1.288 out, 20.125 out,
//  and a load clock at 1/8th that, or 2.515625, but only a small pulse	
//  Author:  Andrew Iverson
//  Date:  11-21-99
//
//--------------------------------------------------

module clk_mod(load_clk, slow_clk, clk1x, clk40x, n_reset);

  output load_clk, slow_clk, clk1x;
  input clk40x, n_reset;

  reg load_clk_temp, slow_clk_temp, clk1x_temp, slck_en;
  reg [4:0] count32, count1x;
  reg [2:0] load_count;

  assign load_clk = load_clk_temp;
  assign slow_clk = slow_clk_temp;
  assign clk1x = ~clk1x_temp;

  always @ (posedge clk40x or negedge n_reset)
  begin
    if (!n_reset)
    begin
      count32 <= 5'b00000;
      count1x <= 5'b00000;
      slow_clk_temp <= 1'b0;
      clk1x_temp <= 1'b0;
	  slck_en <= 1'b0;
    end
    else
     begin 
      // Have clken occur with TC, not after.  This enables the /32 
      //counter for one clock cycle of the clk40x, keeping things 
      // synchronous to the clk40x, not derivations

      slck_en <= (count1x == 5'b10010);

      if (count1x == 5'b10011)
	begin
	 count1x <= 5'b00000;
	 clk1x_temp <= !clk1x_temp;
	end
      else 
	count1x <= count1x + 1'b1;
  
      if(slck_en)
       begin
         if (count32 == 5'b11111)
           begin
	     count32 <= 5'b00000;
	     slow_clk_temp <= ~ slow_clk_temp;
      	   end
         else
           count32 <= count32 + 1; 
       end
     end
  end


  always @ (negedge slow_clk_temp or negedge n_reset)
  begin
    if (!n_reset)
    begin
      load_clk_temp <= 0;
      load_count <= 3'b000;
    end
    else
    begin
      if (load_count == 3'b000)
      begin
	load_count <= load_count + 1'b1;
	load_clk_temp <= 1'b1;
      end
      else
      begin
	load_clk_temp <= 1'b0;
	load_count <= load_count + 1'b1;
      end
    end
  end

endmodule