/* Accumulator 
* Steve Harwood, PSU EE572, Fall 1999
* 
* Take in (6) 12-bit partial products and sum them 
* over five clock cycles (under external control).
* When ld is asserted, pp ta and pp tb are summed, then
* the remaining pp's are accumulated over the next four clocks.
* The accumulator width (17) is large enough to prevent an 
* overflow over the 5 summations, so a carry out is not required.
*/

module acc(ta,tb,tc,td,te,tf,sel,ld,clk,rst,sum);
 input [11:0] ta,tb,tc,td,te,tf;
 input [1:0] sel;
 input ld,clk,rst;

 parameter ACC_WIDTH =17;
 output [ACC_WIDTH-1:0] sum;

 wire [15:0] a;
 wire [11:0] b,t2_5;
 wire [ACC_WIDTH-1 : 0] combsum;

 reg [ACC_WIDTH-1 : 0] sum;

 // Select one of taps 2 through 5
 assign t2_5 = sel[1] ? (sel[0] ? tf: te) : (sel[0]? td:tc); 

 assign a = ld ? {4'h0,ta} : sum[15:0];
 assign b = ld ? tb : t2_5;

 assign combsum = a + {4'h0,b};

 always @(posedge clk or posedge rst)
  begin
   if (rst)
    sum <= 0; 
   else
    sum <= combsum;
  end
endmodule