
\chapter{Evaluation and Applications}
\section{Design Evaluation}

The design of CCM was captured using schematic editor of Xilinx Foundation
Series software, and was implemented on 17 Xilinx XC3090A FPGA chips (see 
Figure \ref{fig:nmap1}) using M1 software from Xilinx. Now that the CCM 
has been verified in its operation, a proper timing analysis must be done
to evaluation of the design of the CCM.

Since our design was mapping on multiple FPGA chips, we will focus
on some paths that span multiple FPGA chips and are likely
to have greater delays. The following paths will be discussed in this section:

\begin{itemize}
\item The path begins from the outputs of registers {\it accu} and
      {\it data}, and goes to the input of the output FIFO. The delay
      of this path is the time that the CCM takes to compute a combinational
      cube operation once the content of registers are set properly.
      This path will be refereed as {\it vertical path}\footnote
{This path just goes through one IT, while the horizontal signals 
like {\it empty} and {\it ready} go through all ITs.}
      in the following section.
\item The {\it counter carry path} includes the entire iterative network
      of counter blocks and the circuit that is used to evaluate
      pre-relation. The delay of this path is the time that the CCM takes
      to evaluation the signal {\it pre\_res} (see section~\ref{CHEN-section3.7}) once
      the registers and control signals are set properly.
\item The {\it empty carry path} is the data path used to generate signal
      {\it empty}. The delay of this path is the that time the CCM takes to
      generate the result cube, and then determine whether the resultant
      cube is an empty cube or not once the registers and control signals
      are set properly.
\item The {\it memory path} connects two memory banks (MEM\_A and MEM\_b) 
      and the registers {\it accu} and {\it data}.
\end{itemize}

The delay of the {\it ready} signal will not be discussed here since
our design is already able to handle it (see section~\ref{CHEN-section3.3.3}). Actually,
the delay of {\it ready} signal is approximate to that of the {\it empty
carry path}. Now let us analysis the time characteristics of these paths.

\begin{itemize}
\item The vertical path.

All ITs are mapped in the first column of the matrix of the DEC-PERLE-1.
The output of the ITs (resultant cubes) goes to the output FIFO
through MBusE, SWE, DBusNE, FSW and FifoOutData. The delay of 385 ns is
the greatest delay of this path.

\item The counter carry path.

This path goes to CSW through 4 matrix FPGAs, 3 segments of matrix
direct connections, MBusS, SWS and RingSW. The delay of 643 ns is
the greatest delay of this path.

\item The empty carry path

This path goes to CSW through 4 matrix FPGAs, 3 segments of matrix
direct connections and RingMat. The delay of 648 ns is the greatest 
delay of this path.

\item The memory path.

The memory path that connects the memory bank MEM\_A and the registers
goes through RamDataW, SWW and MBusW. This path has a delay of 104 ns. 
The other memory path that connects the memory bank MEM\_B and the 
registers goes through MBusE, one matrix FPGA, MBusS, SWS and RamDataS.
This path has a delay of 160 ns.
\end{itemize}

As we discussed in section~\ref{CHEN-section5.4}, the CCM evaluates pre-relation in
states P2 and P5 of GCU, and this should be done in one clock period.
Therefore, the clock period should be greater than 643ns.

For comparing the performance of the CCM and that of the software 
approach, a program can carry out disjoint sharp operation on two arrays
of cubes was created using C language. Then this program and the CCM are
used to solve the following problems:
\begin{itemize}
\item Three variables problem: $1 \#$ (all minterm with 3 binary variables).
\item Four variables problem: $1 \#$ (all minterm with 4 binary variables).
\item Five variables problem: $1 \#$ (all minterm with 5 binary variables).
\end{itemize}

The C program is compiled by GNU C compiler version 2.7.2, and is run
on Sun Ultra5 workstation with 64MB real memory. The CCM is simulated using
QuickHDL software from Mentor Graphics. We simulated the VHDL model of
CCM, got the number of clocks used to solve the problem, then calculated
the time used by CCM using formula: clock $\times$ clock-period. A clock
of 1.33 MHz (clock period: 750 ns) is used as the clock of the CCM.
The experiential result is shown in Table \ref{tbl:comp1}. 



\begin{table}[H]
\caption{Compare CCM (1.33 MHz) with software approach}
\begin{center}
\begin{tabular}{|c|c|c|c|} \hline
Problem & 3 variables & 4 variables & 5 variables \\ \hline
Ultra5 &  111 usec & 268 usec & 812 usec \\ \hline
CCM &  546 $\times$ 0.75 &  1285 $\times$ 0.75 & 3405 $\times$ 0.75 \\ 
     &  = 409 usec &  = 963.75 usec & = 2553.75 usec \\ \hline
speedup & 0.27 & 0.28 & 0.32 \\ \hline
\end{tabular}
\end{center}
\label{tbl:comp1}
\end{table}


It can be seen from Table \ref{tbl:comp1} that our CCM is about 4 times
slower than the software approach. But, the clock of the CPU of Sun Ultra5
workstation is 270 MHz, which is 206 times faster than the clock of the CCM.
Therefore, we still can say that the design of the CCM is very efficient
for cube calculus operations. 

It also can be seen from Table \ref{tbl:comp1} that the more variables
the input cubes have, the more efficient the CCM is. This is due to the 
software approach need to iterate through one loop for each 
variable that is presented in the input cubes.

However, the clock period of 750ns is too slow. From the state
diagram of the GCU (shown in Figure \ref{fig:state_biu}), it can be found
that the delays of {\it empty carry path} and {\it counter carry path} only
occur in a few states. Thus, if we can just give more time to these states,
then we can speedup the clock of the whole CCM. This is very easy to
achieve: for example, the state P2 of GCU need more time for the delay of 
counter carry path, so add two more states in series between states P2 and P3. 
These two extra states do nothing but give the CCM two more clock periods
to evaluate the signal $prel\_res$, which means that the CCM has 3 clock
periods to evaluate signal $prel\_res$ in state P2 after adding two more
``delay" states. After making similar modifications to all these 
kind of states, the CCM can run against a clock of 4 Mhz (clock period of 
250 ns). The CCM was simulated again, and the result is shown in Table 
\ref{tbl:comp2}.

\begin{table}[H]
\caption{Compare CCM (4MHz) with software approach}
\begin{center}
\begin{tabular}{|c|c|c|c|} \hline
Problem & 3 variables & 4 variables & 5 variables \\ \hline
Ultra5 &  111 usec & 268 usec & 812 usec \\ \hline
CCM &  611 $\times$ 0.25 &  1486 $\times$ 0.25 & 4078 $\times$ 0.25 \\ 
     & = 152.75 usec & = 371.5 usec & = 1019.5 usec \\ \hline
speedup & 0.72 & 0.72 & 0.80 \\ \hline
\end{tabular}
\end{center}
\label{tbl:comp2}
\end{table}


It is very hard to increase the clock frequency again with this mapping
because some other paths like {\it memory path} have delays greater
than 150 ns.

From the above comparison result, we can conclude that a design like CCM with
a complex control unit and complex data path is not good for the architecture
of the DEC-PERLE-1 board. 
It can be seen from our CCM mapping that  since a lot of signals must go
through multiple FPGA chips, this leads to greater signal delays.
For instance, if we can connect the memory banks and the registers 
directly, then the memory path has a delay of only 35 ns. But our current
memory path has a delay of 160 ns. 
Another issue is that XC3090 FPGA is kind of ``old" now (6 to 8 years old
technology). The latest FPGA from Xilinx or other vendors has more 
powerful CLBs and more routing resource, and they are made using deep 
sub-micron process technology.

If we can map the entire CCM inside one FPGA chip, then we can speedup the
CCM from the following aspects:
\begin{itemize}
\item If we map entire CCM into one FPGA chip, the signals do not need
      to go through multiple chips again, which means the routing delay
      is reduced.
\item Since the new FPGA chip has more powerful CLBs and routing resource,
      we can map the CCM denser. This also reduces the routing delays.
\item Since new FPGA chips are made using deep sub-micron technology, the delay
      of CLB and routing wires are both reduced. For example, the delay of
      the CLB of XC3090A is 4.5 ns while the delay of CLB of XC4085XL 
      (0.35 micron technology) is only 1.2 ns. This means that it is very 
      easy to achieve 3 times faster mapping.
\end{itemize}

XC4085XL FPGA, a new FPGA from Xilinx, has a CLB matrix of $56 \times 56$
and up to 448 user I/O pins. The CCM should be able to map into one
XC4085XL FPGA. With this new chip, it should not be difficult to run the 
CCM against a clock of 20 MHz (clock period: 50 ns). This means that our
CCM will be about 4 times faster than the software approach while the 
system clock of the CCM is still 5 times slower than that of the workstation.

As said by the designers of the DEC-PERLE-1 board in paper \cite{pam96}:
{\it PAM technology is currently best applied to low-level, massively
repetitive task such as image or signal processing}. The example 
applications are a long integer multiplier, RSA cryptography and
Fast Hough transform \cite{pam96}. All these applications have no or
very simple control units, and their data paths can be easily pipelined.

The CCM has a complex control unit, and a complex data path. It is
difficult to pipeline the data path of the CCM. Therefore, the DEC-PERLE-1
board is not good for the CCM.


\section{Selected Applications of Cube Calculus Machine}
\label{CHEN-Chapter9}

Many logic minimization software tools such as {\bf ESPRESSO}~\cite{brayton84},
{\bf MIS}, {\bf SIS}~\cite{sispaper} and {\bf EXORCISM-MV-2}~\cite{song93,song93b} may 
benefit from the introduction of the CCM. David W. Foote analyzed how much
the CCM can improve the performance of ESPRESSO-II in his 
thesis~\cite{foote94}. 

The CCM can be used to perform set operation, like set intersection, 
set union, set complement, and set relations such as subset as we
discussed in Chapter~\ref{CHEN-Chapter2}. The CCM can be seen as a machine for set-theoretical
problems when it is configured to process only one variable with many 
possible values. The Examples~\ref{CHEN-Example2.12}
to ~\ref{CHEN-Example2.15} are this kind of examples.

The CCM can also speed up the process of solving small size of the 
satisfiability problem and the tautology problem
\footnote
{Both satisfiability problem and tautology problem are NP-complete
problem, which means we are unlikely to find a polynomial-time
algorithm for solving it exactly. In practice, only small size
NP-complete problems can be solved and it may still be possible to find
near-optimal solutions in polynomial-time using approximation algorithm,
and the near-optimal solutions is often good enough. For more information
about NP-complete problem, please see \cite{algorithm89}.  } 
that are the two most fundamental combinational 
problems used in many research and application areas. As shown in 
\cite{perk98}, these two problems can be used to solve many other 
more complicated problems in CAD, Machine Learning and other fields.
The point here is that we speed up the process of solving small size of
these two problems by speeding up the very basic operator.

\section{Satisfiability Problem}
\label{CHEN-section9.1}

Given a product of terms, each term being a Boolean sum of literals;
the {\it satisfiability problem} is to find any product of literals that
satisfies all terms or prove that such product does not exist.

\noindent
\begin{example}
~\label{CHEN-Example9.1}
\end{example}

\noindent
Find all products of literals that let function 
$f(a,b,c,d) = (\overline{a}+b)(\overline{b}+c)(a+\overline{c})$ be 1.

\noindent
{\bf Solution.}

\noindent
It is very easy to rewrite this problem by multiplying out the
expression as follows:
\begin{align*}
f(a,b,c,d) 
&~ =~ (\overline{a}+b)(\overline{b}+c)(a+\overline{c}) \\
& ~=~ (\overline{a}~\overline{b}~+~\overline{a}c+bc)(a+\overline{c}) \\
& ~=~ abc+ \overline{a}~\overline{b}~\overline{c}
\end{align*}

% Now, remove the duplicated cubes, and use absorption law:
% \begin{equation*}
%  A + AB = A \qquad or \qquad A(A+B) = A
% \end{equation*}
% to simplify the function and obtain:
% \begin{align*}
% f(a,b,c,d) 
% & = ab+abc+ac+bc \\
% & = ab+ac+bc
% \end{align*}
% 
% Therefore, the products of literals that let function $f$ be 1 are $ab$,
% $ac$ and $bc$.

The Covering Problem is used in many two level logic minimization algorithms
(being various improvements and extensions of the classical
{\bf Quine-McCluskey algorithm}~\cite{coud94}) and it can be reduced to the
{\bf Petrick Function 
Minimization Problem}, a special case of satisfiability problem. This means 
that the Covering Problem can be solved by minimizing the Petrick Function.
Let us see the following example.
  
\noindent
\begin{example}
~\label{CHEN-Example9.2}
\end{example}

\noindent
The following is a covering table. The problem is to find the
smallest set of rows that covers all columns.

\begin{table}[H]
%\begin{table}[h]
\begin{center}
\begin{tabular}{c|cccccc} \hline
      & $C_1$ & $C_2$ & $C_3$ & $C_4$ & $C_5$ & $C_6$ \\ \hline
$R_1$ &   X   &   X   &       &   X   &       &   X   \\
$R_2$ &       &       &   X   &   X   &       &   X   \\
$R_3$ &   X   &   X   &       &       &       &       \\
$R_4$ &       &       &   X   &       &   X   &       \\ \hline
\end{tabular}
\end{center}
\end{table}

\noindent
{\bf Solution.}

\noindent
First, let us find all sets of rows that cover all columns.
The column $C_1$ is covered by rows $R_1$ and $R_3$;
the column $C_2$ is covered by rows $R_1$ and $R_3$; 
the column $C_3$ is covered by rows $R_2$ and $R_4$; 
the column $C_4$ is covered by rows $R_1$ and $R_2$; 
the column $C_5$ is covered by row $R_4$; 
the column $C_6$ is covered by rows $R_1$ and $R_2$; 
Therefore, the problem can be solved by solving the following Petrick function ($PF$):

\begin{align*}
PF \equiv 1 \equiv & (R_1+R_3)(R_1+R_3)(R_2+R_4)(R_1+R_2)(R_4)(R_1+R_2) \\
= & (R_1+R_3)(R_2+R_4)(R_1+R_2)(R_4) \\
= & (R_1R_2+R_1R_4+R_2R_3+R_3R_4)(R_1+R_2)(R_4) \\
  & \cdots \\
= & R_1R_4+R_1R_2R_4+R_1R_3R_4+R_2R_3R_4+R_1R_2R_3R_4
\end{align*}

The last sum shows that there are five sets of rows that cover all 
columns: \{$R_1$,$R_4$\}, 
\{$R_1$,$R_2$,$R_4$\}, \{$R_1$,$R_3$,$R_4$\}, \{$R_2$,$R_3$,$R_4$\} 
and \{$R_1$,$R_2$,$R_3$,$R_4$\}. Now use the absorption law $A + AB = A$
to simplify the decision function and obtain $PF = R_1R_4 + R_2R_3R_4$, which means 
\{$R_1$,$R_4$\} is the smallest set of rows that covers all columns.

The above example shows how to reduce the Covering Problem to the 
Petrick function problem. The CCM can be used to multiply out the 
function, then the function can be simplified by the software or 
Sorter/Absorber circuitry that you will find in Chapter~\ref{PAVEL-Chapter1},
~\cite{sorter}. It has to be kept in mind by the reader that
CCM was designed because real life covering problems have matrices
with hundreds of thousands of rows and columns. Because, however the 
number of variables in the CCM is limited, a large problem has to be
first decomposed to many smaller problems that fit the CCM word length
and can be solved by it sequentially.

\section{Tautology Problem}
\label{CHEN-section9.2}

The tautology problem is the verification a logic function to see if it
is always true or not.

\noindent
\begin{example}
~\label{CHEN-Example9.3}
\end{example}

\noindent
Is the function $f(a,b,c,d) = a+b+c+d$ a tautology (always be 1)?

\noindent
{\bf Solution.}

\noindent
If the function $f(a,b,c,d) \equiv 1$, this implies that
$1 \# f(a,b,c,d) = 0$, and the function $f(a,b,c,d)$ is a tautology. 
If $1 \# f(a,b,c,d) \neq 0$, then the function $f(a,b,c,d)$ is not a tautology.

Because $1 \# (a+b+c+d) = \overline{a}~\overline{b}~\overline{c}~\overline{d} \neq 0$, then
the function $f(a,b,c,d)$ is not a tautology. The CCM assembly program used
to solve this problem is very similar to the Example~\ref{CHEN-Example6.9}.


\section{Conclusions and Future Work on CCM}

The concept of Cube Calculus, Cube Calculus Machine and a complete
design of the Cube Calculus Machine have been presented in previous chapters. This is
the first complete design of the CCM that has been done so far.
Further work on CCM is being continued.
The design of the ILU presented above has been accomplished by
many students over the years~\cite{coen93,foote94,zhou95,CHEN}.
In the presented design some important
changes have beed done (like EMPTY block, Pre-relation/pre-operation logic block).

\section{Projects}
\begin{enumerate}
\item
Many variants of ILU have been 
described~\cite{coen93,foote94,zhou95}.
The pre-relation/pre-operation that were missing in~\cite{coen93,foote94,zhou95} have been designed
in~\ref{CHEN}. Can you simplify anything in the presented above machine still maintaining its complete
functionality?
\item
Using the VHDL code of CCM from next chapters, simulate it using
QuickHDL tool from Mentor Graphics.
If you have done changes, write them in VHDL and simulate as well. Draw conclusions.
\item
Extend the CCM assembly language for the CCM.
\item
Realize the test bench for your design.
Explore cube operations by using this model
using our encoding scheme of the CCM instructions.
You still need to think in terms of registers and 
individual instructions of the CCM. There are several 
complete examples given in this book, and they can be used by you as an introduction.
\item Improve and unify the descriptions of cube calculus from previous texts that
are not covered in the previous chapters.
\item Derived another formula for calculate cofactor operation by
using cube calculus than one from Equation~\ref{eq:cofactor}.
\item Mapp your design onto the DEC-PERLE-1 board.
Capture the entire design Xilinx Foundation software, and implement in
XC3090A FPGA chips using Xilinx M1 software.
\item Develop the CCM runtime library (see section~\ref{CHEN-section6.1}).
DEC C++ compiler is required.
\item
Build several complete demo applications of practical use such as tautology, satisfiability, or set covering.
\item Run the demos on benchmark functions.
\end{enumerate}


