--------------------------------------------------------------- -- Four Bit Register Example -- -- weiwang 4.12.98 -- --------------------------------------------------------------- PACKAGE resources IS -- user defined enumerated type TYPE level IS ('X', '0', '1', 'Z'); -- ALIAS level IS X01Z ; -- type for vectors (buses) TYPE level_vector IS ARRAY (NATURAL RANGE <>) OF level; -- subtype used for delays SUBTYPE delay IS time range 0 fs to 1 sec; FUNCTION level_it(char : character) return level; END resources; PACKAGE BODY resources IS FUNCTION level_it(char : character) RETURN level IS begin if char = '0' then return '0'; elsif char = '1' then return '1'; elsif char = 'X' then return 'X'; elsif char = 'Z' then return 'Z'; else return 'X'; end if; end level_it; END resources; USE work.resources.all; ENTITY reg4 IS GENERIC(tprop : delay := 8 ns; tsu : delay := 2 ns); PORT(d : IN bit_vector(3 downto 0); clk : IN bit; q : OUT bit_vector(3 downto 0)); --qn : OUT bit_vector(3 downto 0)); END reg4; ARCHITECTURE behavioral OF reg4 IS BEGIN one : PROCESS (clk) BEGIN IF (clk = '1' AND clk'LAST_VALUE = '0') THEN -- rising clock edge IF (d'STABLE(tsu)) THEN -- check setup FOR i IN 3 DOWNTO 0 LOOP IF (d(i) = '0') THEN -- check valid input data q(i) <= '0' AFTER tprop; --qn(i) <= '1' AFTER tprop; ELSIF (d(i) = '1') THEN q(i) <= '1' AFTER tprop; --qn(i) <= '0' AFTER tprop; END IF; END LOOP; END IF; END IF; END PROCESS one; END behavioral;