-- ENTITIY DECLERATION OF 5 input nor :


     ENTITY nor5 IS
       PORT (i1, i2, i3, i4, i5 : IN BIT; o1 : OUT BIT);
     END nor5;



     -- ARCHITECTURE BODY OF THREE-INPUT NAND :
     --
     ARCHITECTURE single_delay OF nor5 IS
     BEGIN
       o1 <= NOT ( i1 OR i2 OR i3 OR i4 OR i5 ) after 6 ns;
     END single_delay;
     --