library ieee;
use ieee.std_logic_1164.all;


entity mux is port (
	 a:		in  BIT_VECTOR (3 downto 0);
	 b: 		in  BIT_VECTOR (3 downto 0);
         c:             in  BIT;
         o:		out BIT_VECTOR (3 downto 0));
end mux;

architecture behavioral_level of mux is
begin 
multiplex:	process(a,b,c)
begin
	if (c = '1') then
		o <= a;
 	else
		o <= b;
	end if;
end process multiplex;
end behavioral_level;