-- ENTITIY DECLERATION OF 4 bit comparator , modified only detect less than:
-- if A>=B output a_lt_b = 0 ; otherwise a_lt_b = 1 

     ENTITY bit4_comp IS
       PORT (a, b : IN BIT_VECTOR (3 DOWNTO 0);  -- a and b data inputs
             lt   : IN BIT;                      -- previous less than
             a_lt_b:OUT BIT
       );
     END bit4_comp;

-- ITERATIVE ARCHITECTURE OF NIBBLE COMPARATOR :

     ARCHITECTURE iterative OF bit4_comp IS
       COMPONENT comp1
         PORT (a, b, lt : IN BIT; a_lt_b : OUT BIT);
       END COMPONENT;
   
       FOR ALL : comp1 USE ENTITY WORK.bit1_comp (gate_level);
       SIGNAL im : BIT_VECTOR ( 0 TO 2);
       SIGNAL gnd : BIT := '0'; 
       SIGNAL vdd : BIT := '1'; 
     BEGIN
       c0: comp1 PORT MAP (a(0), b(0), gnd, im(0));
       c1to2: FOR i IN 1 TO 2 GENERATE
         c: comp1 PORT MAP (a(i), b(i), im(i*1-1), 
                            im(i*1) );
       END GENERATE;
       c3: comp1 PORT MAP (a(3), b(3), im(2), 
                           a_lt_b);
     END iterative;