CAT policies.
From Nick Iliev
Organization PSU
Date 1995
I'm attaching the source for the 11 .vhd files that
implement the waveform generator for homework #2 :
1. CU2.VHD control unit, signal STATE
2. DU2.VHD datapath unit
3. ADSUB.VHD adder/subtractor , signal SUM
4. MUX1.VHD, multiplexors providing inputs to the ADSUB
MUX2.VHD, under controlled condition;s
MUX3.VHD signal NM1 from mux1
5. CMPR.VHD comparator, signal EQ
6. GENP.VHD generator of predicate conditions for the CU2
7. REGA1.VHD input registers for A,B,C, T1, and T2
output register QZ
8. CNTR.VHD up/down couter, signal CNT
9. TBPLA.VHD test-bentch module, sets
A = "00000011" 3
B = "00001000" 8
C = "00001100" 12
T1 = "111" 7
T2 = "011" 3
10 listfile output of test run;
Currently, the waveform has to be assembled by observing all 3
registers QZ, CNT, and NM1 :
initially, QZ keeps a '3' for T1 clock periods, then after 2 clk
periods, NM1 starts counting up to C=12 in 9 clock periods -
in clock period #18 ( from start of simulation), NM1=1100 (12);
during the next period (# 19), NM1 is switched to QZ, in #20
the counter is reset, CNT=0, and in #21 NM1 starts decrementing
from 12 to 8 (B) , in 4 periods. In #24, NM1 = 1000 (8), in #25
NM1 is switched again in QZ, in #26 CNT=0, and for the next T2
periods, #27, #28, #29, QZ is held at 1000 (B) . During periods
#30 and #31, the controller is reset to state S0, ready for another
round. In my next revision of the code, QZ will display the entire
continuous waveform, instead of a piecewise-linear approximation with
QZ and NM1.
--
Nick
next from Nick Iliev
--- TBPLA.VHD ----
entity TBPL is
end TBPL;
use work.all;
architecture FR of TBPL is
signal c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13 :BIT;
signal p0,p1,p2,p3,p4,RUN,CLK : BIT;
signal DA,DB,DC,DT1,DT2,QZ : BIT_VECTOR (7 downto 0);
component CLKG
port ( RUN : in BIT; CLK : out BIT);
end component;
component DPT
port (c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13 :in BIT;
RUN : in BIT; CLK : in BIT;
DA,DB,DC,DT1,DT2 : in BIT_VECTOR(7 downto 0);
p0,p1,p2,p3,p4 : inout BIT; QZ : inout BIT_VECTOR (7 downto 0) );
end component;
component CP
port (p0,p1,p2,p3,p4,CLK : in BIT;
c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13 : inout BIT);
end component;
for L1 : DPT use entity DP2 (RTL);
for L2 : CP use entity CU2 (RTL);
for L3 : CLKG use entity CLOCK_GEN (ALG);
begin
L1 : DPT
port map ( c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,RUN,CLK,
DA,DB,DC,DT1,DT2,p0,p1,p2,p3,p4,QZ);
L2 : CP
port map (p0,p1,p2,p3,p4,CLK,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,
c11,c12,c13 );
L3 : CLKG
port map (RUN, CLK);
process
begin
DA <= "00000011" after 2 ns;DB<="00001000" after 2 ns;
DC<="00001100" after 2 ns;
DT1 <="00000111" after 2 ns;DT2 <="00000011" after 2 ns;
RUN <= '1' after 5 ns, '0' after 650 ns;
wait;
end process;
end FR;
********************* DU2.VHD ***********************
entity DP2 is
port ( c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,
c12,c13,RUN,CLK : in BIT;DA,DB,DC,DT1,DT2 : in BIT_VECTOR(7 downto 0);
p0, p1,p2,p3,p4 : out BIT ;QZ : inout BIT_VECTOR(7 downto 0) );
end DP2;
use work.all;
architecture RTL of DP2 is
signal EQ,S1,S2,S3 : BIT;
signal CNT,NM1,NM2,NM3,SUM : BIT_VECTOR ( 7 downto 0);
signal QA1,QB1,QC1,QTA,QTB: BIT_VECTOR ( 7 downto 0);
signal RESET,COUNT,LOAD : BIT;
component GENP1
port (c7,c11,c12,c6,EQ : in BIT; p1,p2,p3,p4 : out BIT);
end component;
component CNTR1
port (RESET,COUNT,CLK: in BIT; CNT: inout BIT_VECTOR(7 downto 0));
end component;
component MX1
port ( I1,I2,I3,I4,CLK : in BIT; N,M,SUM1: in BIT_VECTOR( 7 downto 0);
NM1 : inout BIT_VECTOR( 7 downto 0));
end component;
component MX2
port ( I1,I2,I3,I4 : in BIT;N,M: in BIT_VECTOR( 7 downto 0);
NM2 : inout BIT_VECTOR(7 downto 0) );
end component;
component MX3
port ( I1,I2,I3,I4,I5,I6,I7,I8 : in BIT; N,M,L : in BIT_VECTOR( 7 downto 0);
NM3 : inout BIT_VECTOR (7 downto 0) );
end component;
component ADS
port ( A,B : in BIT_VECTOR ( 7 downto 0); SUM : inout BIT_VECTOR (7 downto 0);
c11,c10,c13,c12 : in BIT );
end component;
component COMP1
port ( N,M :in BIT_VECTOR( 7 downto 0); EQ : inout BIT);
end component;
component REGA
port ( LOAD,CLK : in BIT; DATA_IN: in BIT_VECTOR( 7 downto 0);
QA1 : inout BIT_VECTOR( 7 downto 0) );
end component;
component REGB
port ( LOAD,CLK : in BIT; DATA_IN: in BIT_VECTOR( 7 downto 0);
QB1 : inout BIT_VECTOR (7 downto 0) );
end component;
component REGC
port ( LOAD,CLK : in BIT; DATA_IN: in BIT_VECTOR( 7 downto 0);
QC1 : inout BIT_VECTOR ( 7 downto 0) );
end component;
component RTA
port ( LOAD,CLK : in BIT; DATA_IN: in BIT_VECTOR( 7 downto 0);
QTA : inout BIT_VECTOR ( 7 downto 0 ));
end component;
component RTB
port ( LOAD,CLK : in BIT; DATA_IN: in BIT_VECTOR( 7 downto 0);
QTB : inout BIT_VECTOR ( 7 downto 0 ));
end component;
component RTZ
port ( LOAD,RESET,CLK,c11L,c12L, EQL : in BIT; DATA_IN: in BIT_VECTOR( 7 downto 0);
SUM1 : in BIT_VECTOR( 7 downto 0);
QZ : inout BIT_VECTOR ( 7 downto 0 ));
end component;
for L1 : GENP1 use entity GENP (DF);
for L2 : CNTR1 use entity COUNTER(ALG);
for L3 : MX1 use entity MUX1 (NORDF);
for L4 : MX2 use entity MUX2 (NORDF);
for L5 : MX3 use entity MUX3 (NORDF);
for L6 : ADS use entity AD_AB (ALG);
for L7 : COMP1 use entity CMP (NORDF);
for L8 : REGA use entity REGA1 (DF);
for L9 : REGB use entity REGB1 (DF);
for L10 : REGC use entity REGC1 (DF);
for L11 : RTA use entity REGTA (DF);
for L12 : RTB use entity REGTB (DF);
for L13 : RTZ use entity REGZ (DF);
begin
L1 : GENP1
port map ( c7,c11,c12,c6,EQ,p1,p2,p3,p4);
L2 : CNTR1
port map (c8,c6,CLK,CNT);
L3 : MX1
port map (c11,c12,c10,c13,CLK,QZ,QC1,SUM,NM1);
L4 : MX2
port map (c10,c13,c11,c12,QA1,QB1,NM2);
L5 : MX3
port map (c11,c12,c6,c7,c12,c11,c7,c6,SUM,QTA,QTB,NM3);
L6 : ADS
port map (NM1,NM2, SUM,c11,c10,c13,c12);
L7 : COMP1
port map (CNT,NM3,EQ);
L8 : REGA
port map (c1,CLK,DA,QA1);
L9 : REGB
port map (c2,CLK,DB,QB1);
L10 : REGC
port map (c3,CLK,DC,QC1);
L11 : RTA
port map (c4,CLK,DT1,QTA);
L12 : RTB
port map (c5,CLK,DT2,QTB);
L13 : RTZ
port map (c7,c9,CLK,c11,c12,EQ,QA1,NM1,QZ);
process (RUN, CLK)
begin
if RUN = '1' then p0 <='1' ; else p0 <='0'; end if;
end process;
end RTL;
************************* CU2.VHD ***************************
entity CU2 is
port ( p0,p1,p2,p3,p4,CLK : in BIT;
c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13: out BIT );
end CU2 ;
architecture RTL of CU2 is
type STATE_TYPE is (S0,S1, S2, S3,S4,S5,S6,S7,S8,S9 );
signal STATE: STATE_TYPE;
begin
TRANSIT: process (CLK)
begin
if CLK = '1' then
case STATE is
when S0 =>
if p0 = '0' then
STATE <= S0;
elsif p0 = '1' then
STATE <= S1;
end if;
when S1 =>
if p1 = '1' then
STATE <= S3;
elsif p1 = '0' then
STATE <= S2;
end if;
when S2 =>
if p1 = '1' then
STATE <= S3;
elsif p1 = '0' then
STATE <= S2;
end if;
when S3 =>
STATE <= S4;
when S4 =>
if p2 = '0' then
STATE <= S4;
elsif p2 = '1' then
STATE <= S5;
end if;
when S5 =>
STATE <= S6;
when S6 =>
if p3 = '0' then
STATE <= S6;
elsif p3 = '1' then
STATE <= S7;
end if;
when S7 =>
STATE <= S8;
when S8 =>
if p4 ='0' then
STATE <= S8;
elsif p4 = '1' then
STATE <= S9;
end if;
when S9 =>
STATE <= S0;
end case;
end if;
end process TRANSIT;
OUTPUT : process (STATE)
begin
case STATE is
when S0 =>
if p0 = '0' then c1<='0';c2<='0';c3<='0';c4<='0';
c5<='0';c6<='0';c7<='0';c8<='0';c9<='0';
c10<='0';c11<='0';c12<='0';c13<='0';end if;
when S1 =>
if p0 = '1' then c1 <= '1'; c2 <= '1';c3<='1';c4<='1';
c5<='1';c8<='1';c9<='1';end if;
when S2 =>
if p1 = '0' then c6<='1';c7<='1';c1<='0';c2<='0';c3<='0';
c4<='0';c5<='0';c8<='0';c9<='0'; end if;
when S3 =>
if p1 = '1' then c10<='1';c8<='1';c1<='0';c2<='0';
c3<='0';c4<='0';c5<='0';c6<='0';c7<='0';
c9<='0';c11<='0';c12<='0';end if;
when S4 =>
if p2 = '0' then c6<='1'; c11<='1'; c10<='0';c8<='0'; end if;
when S5 =>
if p2 = '1' then c8<='1';c13<='1';c6<='0';c11<='0';end if;
when S6 =>
if p3 = '0' then c6<='1';c12<='1';c8<='0';c13<='0';end if;
when S7 =>
if p3 = '1' then c8<='1';c6<='0';c12<='0';end if;
when S8 =>
if p4='0' then c6<='1';c8<='0'; end if;
when S9 =>
if p4 = '1' then c9<='1'; c6<='0'; end if;
end case;
end process OUTPUT;
end RTL;
***************************** ADSUB.VHD *********************************
-- Adder or Subtract two 8-bit vectors
--
entity AD_AB is
port (A, B : in BIT_VECTOR(7 downto 0 ); SUM : out BIT_VECTOR(7 downto 0);
c11,c10,c13,c12 : in BIT);
end AD_AB;
architecture ALG of AD_AB is
begin
AB: process (A,B)
variable vSUM,LA,RB : BIT_VECTOR( 7 downto 0);
variable CAR : BIT;
begin
if c11 = '1' then -- setup for addition
LA := A;RB := B; CAR:= '0';
elsif (c10 or c13 or c12) = '1' then -- setup for subtracting
LA := A; RB:= not B; CAR :='1';
end if;
for I in 0 to vSUM'HIGH loop
vSUM(I) := LA(I) xor RB(I) xor CAR;
CAR := ( LA(I) and RB(I) ) or ( LA(I) and CAR) or
( CAR and RB(I));
end loop;
-- Cout <= CAR;
SUM <= vSUM;
end process AB;
end ALG;
******************************** MUX3.VHD *************************************
-- Mux for 3 8-bit vectors
--
entity MUX3 is
port ( I1,I2,I3,I4,I5,I6,I7,I8 : in BIT; N,M,L : in BIT_VECTOR(7 downto 0);
NM3 : out BIT_VECTOR ( 7 downto 0));
end MUX3;
use work.all;
architecture NORDF of MUX3 is
begin
process (I1,I2,I3,I4,I5,I6,I7,I8 )
variable S1, S2, S3 : BIT;
begin
S1 := I1 or I2;S2 := I3 and I4;
S3 := (not I5) and (not I6) and (not I7) and I8;
if ( S1 = '1' and S2 = '0' and S3 = '0') then NM3 <= N ;
elsif (S1 = '0' and S2 = '1' and S3 = '0') then NM3 <= M ;
elsif (S1 = '0' and S2 = '0' and S3 = '1') then NM3 <= L ;
else NM3 <= "00000000" ;
end if;
end process;
end NORDF;
*************************** MUX2.VHD ********************
-- Mux for 3 8-bit vectors
--
entity MUX2 is
port ( I1,I2,I3,I4: in BIT; N,M : in BIT_VECTOR(7 downto 0);
NM2 : out BIT_VECTOR ( 7 downto 0));
end MUX2;
use work.all;
architecture NORDF of MUX2 is
begin
process (I1,I2,I3,I4 )
variable S1, S2, S3 : BIT;
begin
S1 := I1; S2 := I2; S3:= I3 or I4;
if S1 = '1' and S2 = '0' and S3 = '0' then NM2 <= N ;
elsif S1 = '0' and S2 = '1' and S3 = '0' then NM2 <= M ;
elsif S1 = '0' and S2 = '0' and S3 = '1' then NM2 <= "00000001" ;
else NM2 <= "00000000" ;
end if;
end process;
end NORDF;
************************ MUX1.VHD **************************
-- Mux for 2 8-bit vectors
--
entity MUX1 is
port ( I1,I2,I3,I4,CLK: in BIT;N,M,SUM1 : in BIT_VECTOR(7 downto 0);
NM1 : inout BIT_VECTOR ( 7 downto 0));
end MUX1;
use work.all;
architecture NORDF of MUX1 is
begin
process (I1,I2,I3,I4,CLK )
variable S1,S2 : BIT;
variable LZ : BIT:= '0';
begin
S1 := I1 or I2; S2 := I3 or I4;
if S1 = '1' and S2 = '0'
then
if LZ = '0' and CLK = '1' and (not CLK'STABLE) then
NM1 <= SUM1;
elsif LZ = '1' then
NM1 <= N; LZ := '0';end if;
elsif S2 = '1' and S1 = '0' then NM1 <= M ;LZ:='1';
else NM1 <= NM1 ; end if;
end process;
end NORDF;
************************** CMPR.VHD ***********************************
-- Comparator module - two 8-bit vectors
--
use work.all;
entity CMP is
port ( N,M : in BIT_VECTOR(7 downto 0);
EQ : out BIT);
end CMP;
use work.all;
architecture NORDF of CMP is
begin
process (N,M)
variable Z2,Z1, Z0: BIT_VECTOR(7 downto 0);
begin
Z2 := N; Z1:=M;
for I in 0 to Z1'HIGH loop
Z0(I) := not(Z2(I) xor Z1(I) ) ;
end loop;
EQ <= Z0(0) and Z0(1) and Z0(2) and Z0(3) and Z0(4) and
Z0(5) and Z0(6) and Z0(7);
end process;
end NORDF;
************************* GENP.VHD ************************************
use work.all;
entity GENP is
port ( c7,c11,c12,c6, eq : in BIT; p1,p2,p3,p4: out BIT);
end GENP;
architecture DF of GENP is
begin
p1 <= c7 and eq;
p2 <= c11 and eq;
p3 <= c12 and eq;
p4 <= ( (not c12) and (not c11) and( not c7) and c6 ) and eq;
end DF;
************************* REGA1.VHD ******************************
-- Registers -
-- A1
use work.all;
entity REGA1 is
port (LOAD, CLK : in BIT; DATA_IN: in BIT_VECTOR(7 downto 0);
QA1: inout BIT_VECTOR( 7 downto 0)) ;
end REGA1;
architecture DF of REGA1 is
begin
REG: block(not CLK'STABLE and CLK = '1')
begin
QA1 <=
guarded DATA_IN when LOAD = '1' else
QA1;
end block REG;
end DF;
use work.all;
entity REGB1 is
port (LOAD, CLK : in BIT; DATA_IN: in BIT_VECTOR(7 downto 0);
QB1: inout BIT_VECTOR( 7 downto 0)) ;
end REGB1;
architecture DF of REGB1 is
begin
REG: block(not CLK'STABLE and CLK = '1')
begin
QB1 <=
guarded DATA_IN when LOAD = '1' else
QB1;
end block REG;
end DF;
entity REGC1 is
port (LOAD, CLK : in BIT; DATA_IN: in BIT_VECTOR(7 downto 0);
QC1: inout BIT_VECTOR( 7 downto 0)) ;
end REGC1;
architecture DF of REGC1 is
begin
REG: block(not CLK'STABLE and CLK = '1')
begin
QC1 <=
guarded DATA_IN when LOAD = '1' else
QC1;
end block REG;
end DF;
entity REGTA is
port (LOAD, CLK : in BIT; DATA_IN: in BIT_VECTOR(7 downto 0);
QTA: inout BIT_VECTOR( 7 downto 0)) ;
end REGTA;
architecture DF of REGTA is
begin
REG: block(not CLK'STABLE and CLK = '1')
begin
QTA <=
guarded DATA_IN when LOAD = '1' else
QTA;
end block REG;
end DF;
entity REGTB is
port (LOAD, CLK : in BIT; DATA_IN: in BIT_VECTOR(7 downto 0);
QTB: inout BIT_VECTOR( 7 downto 0)) ;
end REGTB;
architecture DF of REGTB is
begin
REG: block(not CLK'STABLE and CLK = '1')
begin
QTB <=
guarded DATA_IN when LOAD = '1' else
QTB;
end block REG;
end DF;
entity REGZ is
port (LOAD,RESET, CLK,c11L,C12L,EQL : in BIT; DATA_IN: in BIT_VECTOR(7 downto 0);
SUM1 : in BIT_VECTOR ( 7 downto 0);
QZ: inout BIT_VECTOR( 7 downto 0)) ;
end REGZ;
architecture DF of REGZ is
begin
REG: block(not CLK'STABLE and CLK = '1')
begin
QZ <= guarded "00000000" when RESET = '1' else
DATA_IN when LOAD = '1' else
SUM1 when (c11L = '1' or C12L ='1') and EQL = '1' else
QZ;
end block REG;
end DF;
************************ CNTR.VHD **************************
-- Counter and Clock modules
--
use work.all;
entity COUNTER is
port (RESET,COUNT,CLK : in BIT;
CNT : inout BIT_VECTOR(7 downto 0));
end COUNTER ;
architecture ALG of COUNTER is
function INC(X : BIT_VECTOR) return BIT_VECTOR is
variable XV: BIT_VECTOR(X'LENGTH-1 downto 0);
begin
XV := X;
for I in 0 to XV'HIGH loop
if XV(I) = '0' then
XV(I) := '1';
exit;
else XV(I) :='0';
end if;
end loop;
return XV;
end INC;
begin
process (CLK)
begin
if CLK = '1' then
if RESET = '1' then CNT <= "00000000";
elsif COUNT = '1' then CNT <= INC(CNT);
end if;
end if ;
end process;
end ALG;
entity CLOCK_GEN is
port (RUN : in BIT; CLK : out BIT);
end CLOCK_GEN;
architecture ALG of CLOCK_GEN is
signal CLOCK : BIT;
begin
process (RUN,CLOCK)
variable CLKE : BIT:='0';
begin
if RUN = '1' and not RUN'STABLE then
CLKE := '1';
CLOCK <= transport '0' after 5 ns;
CLOCK <= transport '1' after 10 ns;
end if;
if RUN = '0' and not RUN'STABLE then
CLKE := '0';
end if;
if CLOCK = '1' and not CLOCK'STABLE and CLKE= '1' then
CLOCK <= transport '0' after 5 ns;
CLOCK <= transport '1' after 10 ns;
end if;
CLK <= CLOCK;
-- if rCLKE = '1' then CLKE := '0'; end if;
end process;
end ALG;
***************************** LISTFILE A=3, B=8, C=12, T1=7, T2 = 3 *****************
ns delta clk qz cnt nm1 state eq c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 p0 p1 p2 p3 p4
0 +0 0 00000000 00000000 00000000 s0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 +1 0 00000000 00000000 00000000 s0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
5 +1 0 00000000 00000000 00000000 s0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
15 +1 1 00000000 00000000 00000000 s0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
15 +2 1 00000000 00000000 00000000 s1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
15 +3 1 00000000 00000000 00000000 s1 1 1 1 1 1 1 0 0 1 1 0 0 0 0 1 0 0 0 0
20 +1 0 00000000 00000000 00000000 s1 1 1 1 1 1 1 0 0 1 1 0 0 0 0 1 0 0 0 0
25 +1 1 00000000 00000000 00000000 s1 1 1 1 1 1 1 0 0 1 1 0 0 0 0 1 0 0 0 0
25 +2 1 00000000 00000000 00000000 s2 1 1 1 1 1 1 0 0 1 1 0 0 0 0 1 0 0 0 0
25 +3 1 00000000 00000000 00000000 s2 1 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0
25 +4 1 00000000 00000000 00000000 s2 1 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0
25 +5 1 00000000 00000000 00000000 s2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0
25 +6 1 00000000 00000000 00000000 s2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0
30 +1 0 00000000 00000000 00000000 s2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0
35 +1 1 00000000 00000000 00000000 s2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0
35 +2 1 00000011 00000001 00000000 s2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0
40 +1 0 00000011 00000001 00000000 s2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0
45 +1 1 00000011 00000001 00000000 s2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0
45 +2 1 00000011 00000010 00000000 s2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0
50 +1 0 00000011 00000010 00000000 s2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0
55 +1 1 00000011 00000010 00000000 s2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0
55 +2 1 00000011 00000011 00000000 s2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0
60 +1 0 00000011 00000011 00000000 s2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0
65 +1 1 00000011 00000011 00000000 s2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0
65 +2 1 00000011 00000100 00000000 s2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0
70 +1 0 00000011 00000100 00000000 s2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0
75 +1 1 00000011 00000100 00000000 s2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0
75 +2 1 00000011 00000101 00000000 s2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0
80 +1 0 00000011 00000101 00000000 s2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0
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