Marek A. Perkowski, Professor EE.
NEW CLASS ANNOUNCEMENT FOR WINTER QUARTER.
CONTROL UNIT DESIGN. EE 573/ EE 673.
This class is a totally redesigned class.
No prerequisities necessary.
New students can be addmitted.
New material related to FPGAs is added.
Book written by the professor is now made available.
BOOKS USED.
Zvi Kohavi, "Switching and Finite Automata Theory." Chapters 9 - 16. THIS IS THE MAIN TEXTBOOK.
P. Ashar, S. Devadas, R. Newton, "Sequential Logic Synthesis". Chapters 3 - 5.
Marek Perkowski, "Design, Test and Verification of Sequential Circuits." available from the author. Whole book.
your remarks will help me to improve this book.
G. DeMicheli, same book as in EE 572, for reference.
Hachtel and Somenzi, same book as in EE 572, for reference.
GRADING.
Two Homeworks: they are student project reports, initial and final,
and student class presentations. No exams.
Some homeworks will include creating WWW Pages related to class topics and using
state machine and sequential circuit synthesis/analysis/testability software.
List of projects is available on
class web page.
Grading Policy:
Initial project proposal: 20 %.
Quality of class presentation and related WWW pages: 15 %.
Final Project Description: 65 %.
MEETINGS.
Class will be taught at PSU, in the evenings, Mondays and Wednesdays,
8:15PM (20:15), room 6008, FAB, which means, Fourth Avenue Building.
You need your student ID card to get access to the building after 8pm.
ADDITIONAL MEETINGS.
There will be additional meetings, reading/rehearsal
group that will meet to discuss the material.
If you are not sure if your background is sufficient,
these meetings should help you. We will solve problems and discuss papers.
It will be also scheduled in evenings.
These meetings will be on Thursdays, 6pm, 6008, FAB, which means, Fourth Avenue Building.
SEMINARS.
There are seminars of our research
group, Fridays, 4pm, room SA60, SEAS ANNEX BUILDING.