LATTICE DIAGRAMS AND THEIR GENERALIZATIONS

  1. PROFESSOR: Marek A. Perkowski

LAYOUT-DRIVEN LOGIC SYNTHESIS FOR FINE-GRAIN FPGAS AND SUB-MICRON TECHNOLOGIES.


  1. Lattice Diagrams using Shannon and Davio expansions.
    Please read the respective materials in papers about layout-driven logic synthesis for sub-micron technologies
  2. OTHER APPROACHES: Please read Gueesang Lee, Logic Synthesis for Cellular Architecture FPGA using BDD
  3. FPGAs and synthesis for FPGAs.
  4. Please read report of Ben Drucker, Craig Files, and Peter Siracusa on Symmetry in Layout
  5. Please read Nan Zhuang, and Peter Y.K. Cheung, "Using Genetic Algorithm in Binate Covering for LUT-based FPGA Technology Mapping"
  6. Please read Nan Zhuang, and Peter Y.K. Cheung, "Logic Synthesis for a Fine-grain, Dynamically Reconfigurable FPGA,"

INTRODUCTION TO REED-MULLER LOGIC AND LINEARLY INDEPENDENT LOGIC.

  1. EXOR logic and decision diagrams.
  2. Please read Song Ning, Marek Perkowski, IEEE Trans. on CAD paper on ESOP Minimizer EXORCISM-MV-2.
  3. Please read Song Ning, Marek Perkowski, New paper on EXORCISM-MV-3.


  4. Experiences of using Evolutionary Techniques in Logic Minimisation, by Julian F. Miller, Peter V. G. Bradbeer, Peter Thomson

    Zilic's Papers Zakrevskij Approach
  5. Please read M.Perkowski, A.Sarabi,F.R.Beyl, "Universal XOR Canonical Forms of Boolean Functions and its Subset Family of AND/OR/XOR Canonical Forms", paper from IWLS'95
  6. Please read B. Becker, R. Drechsler, "How many Decomposition Types do we need?".
  7. Please read B. Becker, R. Drechsler, M. Theobald, "Minimization of 2-level AND/XOR Expressions using Ordered Kronecker Functional Decision Diagrams

  8. Please read R. Drechsler, B. Becker, A. Jahnke, "On Variable Ordering and Decomposition Type Choice in OKFDDs,"
  9. Open Problems in EXOR logic for project.
  10. PROJECT NUMBER THREE:
    ``Exact solution to Generalized Zakrevskij Staircase Method for Search problems for strongly unspecified functions, in particular ESOP and Galois ESOP.''