Electrical Engineering Department
Portland State University
MENTOR TOOLS TUTORIAL SESSION #4
Douglas V. Hall
Electrical Engineering Department
Portland State University
P.O Box 751
Portland OR, 97207
In the preceding tutorial sessions we showed you how to access the Mentor manuals with the BOLD Browser, how to draw the schematic for a circuit with Design Architect, and how to verify the logic and timing of a circuit with QuickSimII. One major goal of this tutorial is to give you further practice with these tools and add a few more useful techniques. In some cases you may want to refer to one of the preceding tutorials if the details of how you perform a specified action have faded in your memory.
A second major goal of this session is to show you how to simulate a design containing a state machine implemented with a programmable logic device. This involves loading the JEDEC file for the programmable device and forcing the state machine into a known state at the start of the simulation.
The third major goal of this tutorial is to show you how to use a do file to set up the simulator so that you do not have to add traces, lists, and forces each time you invoke the simulator during a design spin.
At the conclusion of this session you should be able to:
- Use the Navigator to copy a design.
- Add reference identifiers to the devices in a schematic.
- Include a PLD in a design and "program" the PLD by attaching a JEDEC filename to the model for the device.
- Add force commands necessary to put a state machine in a known state at the start of a simulation.
- Create and execute a "do" file which adds traces, a list, and forces to a design for simulation.
Down load the figure
- In this tutorial you will add a GAL16V8 PLD to a copy of the spike1 decoder circuit
you drew in
To "program" or initialize this device so that it functions as a counter, you will need the appropriate fusemap (.jed) file. To make your life easier, this file has been created for you. After you log on, enter the command:
cp ~dough/public/count10.jed count10.jed
to copy this file to your home directory for future reference.
- Enter the "setenv MGC_WD /u/your_user_name" command. Bring up the Design Manager by entering the "dmgr" command.
After Design manager appears, enlarge the window by dragging the lower right corner down and to the right with the mouse.
COPYING A DESIGN
In the overall design process, once you get a working design, it is a good idea to leave that design untouched and experiment further with a copy of that design. You cannot use the unix cp command to make a copy of a design directory, because the cp command does not adapt the design links as required.
There are several ways to correctly copy a design. For this tutorial you will use the Navigator COPY command to copy the spike1 design you made in
to a new design directory called bcd. For more complex design copy operations it is easier to pop up the banner MGC menu and select the -Design Management-Copy Object command.
- In the center window of Design Manager, click on the file-folder shaped icon labeled spike1 to select it.
- Click on the COPY button in the Navigator window of Design Manager.
- When the small form appears in the lower left corner of the Design Manager window, enter bcd as the name for the copy and click on OK.
- Wait for the copy successful message at the bottom of the window before proceeding.
USING DESIGN ARCHITECT TO MODIFY THE SCHEMATIC
- In the Design Manager Tools window, click on the Design Architect icon to activate it, pop up the Tool operations menu, and choose Open to bring up Design Architect. When the Design Architect window is in place, enlarge it by using the mouse to drag the lower right corner of the window down and to the right.
- Click the left mouse key on the OPEN SHEET icon in the Session _palette of the Design Architect window. When the Open Sheet form appears, enter /u/your_user_name/bcd as the Component Name and then click on the OK button. When the bcd sheet window appears, expand it to maximum. Note that since this is a copy of an old design, the grid parameters are already set to 0.100 so you don't have to set these as you do when creating a new schematic.
- The first modification of this schematic is to edit the title box so it contains the new design name and date. Pop up the banner View menu and choose View Area. Use the mouse and the left mouse key to make a box which contains the title block, then release the mouse key.
- Before you can edit the text, you have to select it. To do this, put the cursor in the schematic window and press the right mouse key to pop up a menu. Go to the Other Menus -Properties/Text menu, choose Select-Area-Comment Text, and release the mouse key. Click the left mouse key on Spike1 in the title block.
- Pop up the Property/Text menu again, and choose Change Value. When the small form appears at the bottom of the screen, replace spike1 with bcd and click on OK. Pop up the Property/Text menu again and choose unselect to unselect the new title.
- Repeat steps 4 and 5 to put the correct date in the title block.
- Use the banner View-View All command to see the complete schematic in the window.
- The next major operation here is to modify the schematic so that it is similar to the attached Figure 1. As a first step, you may have to move the spike1 part of the circuit so there is room for the GAL16V8 PLD. To select the entire block of circuitry so you can move it, put the cursor above and to the left of the block, hold down the left mouse key, drag the mouse down and to the right until all the circuitry is enclosed, then release the mouse key. To actually move the block, put the cursor in the schematic window, pop up the Mixed Selection menu and choose Move. Use the mouse to move the selected block to the desired location and click the left mouse key to place it there. Then pop up a menu and choose Unselect - All.
- For this schematic you will again be using components from two major libraries. For the programmable logic device you will be using a model from Logic Modeling Corporation which is accessed through the Libraries entry at the top of the Design Architect window. For Vcc, ground, portin, and portout connectors you will be using the Mentor Graphics misc_lib which is accessed through the LIBRARY icon in the schematic_palette window.
Move the cursor to the Libraries entry at the top of the Design Architect window, pop up the menu, and choose LMC SmartModels. A list of the major LMC component sub-libraries should appear in the right window. Click on the Programmable Logic entry. After reading the listing for the Programmable Logic click on the 20-pin PAL entry. In the 20-pin PAL listing click on Lattice. In the Lattice listing click on 16V8GAL. Finally, in the 16V8 listing click on GAL16V8A-25L. Note: you may have to pop up a window in the list and click on Show Scroll Bars, so you can scroll down to the 16V8A-25L in the list.
- Move the cursor into the schematic window, position the ghost of the GAL16V8A at an appropriate location to the left of the spike1 circuitry, and click the left mouse key to place (instantiate) it.
- It is about time to make a backup copy of your work, so pop up the banner File menu and choose Save sheet.
COMPLETING THE SCHEMATIC
- Use the banner View-View Area command and the mouse to show just the section of the schematic which contains the area around the PLD and the Portin connectors for the spike1 section.
- If the Schematic-palette menu is not present in the right window, put the cursor in a blank section of the right window, pop up the Palette menu, and choose Show Schematic_palette. Click on the LIBRARY icon and, when the MGC Digital Libraries list appears, click on the misc_lib entry. Note: Again, you may have to pop up a menu and choose Show Scroll Bars so you can scroll down to this entry.
- From the misc_lib, get and place portin connectors for the clk, clr, and dir inputs as shown in the accompanying Figure 1. Then get and place portout connectors for the carry and borrow signals as also shown in the accompanying figure. Finally, get a ground symbol for the unused inputs of the PLD.
- Now you want to add nets to complete the circuit as shown in the accompanying figure. Pop up the schematic window Add menu and choose Wire. When the + cursor appears, put it on one end of a desired net and click the left mouse key. Drag the net to the desired end point and double click the left mouse key to end the net. Note: When drawing nets, remember to move the cursor with the rhythm of the system response or you will put nets everywhere but where you want them.
When you finish drawing all the nets, press the Esc key to exit the net drawing mode, then save the sheet.
- To change the names on the Portin and Portout connectors, pop up the banner Edit- Edit Commands - Properties menu and choose Change Text Values. When the Change Text Values form appears, put the cursor in the Text Value box and type clr.
Another box will appear under the clr box. Move the cursor into this box and type dir. Type clk in the third box, borrow in the fourth box, and carry in the fifth box. Click on OK.
Place the cursor in the center of the NET label next to the top PORTIN connector and click the left mouse key. clr should replace the NET label. Place the cursor on the NET label next to the portin connector second from the top and click the left mouse key again. dir should replace the NET here. Repeat for the rest of the connectors.
- Next, you want to change the reference identifiers on the IC's from U? to something more meaningful. The easiest way to do this is the same way you changed the names of the portin and portout connectors. Pop up the banner Edit - Edit Commands- Properties menu and choose Change Text Value. When the form appears, enter U1 in the first box, enter U2a, U2b, U2c, and U2d in the next four boxes, then enter U3a, U3b, and U3c in the next three boxes, and click on OK. Click on the U? label at the top of the GAL16V8A to change its reference identifier to U1. Click on each identifier in turn to identify the ICs as shown in the attached Figure 1.
- Finally, you have to attach the fusemap(JEDEC) file for the BCD counter to the GAL16V8A model so that it will simulate correctly. Select the GAL16V8, then pop up the banner Edit - Edit Commands - Properties menu and choose Modify. Read the form that appears to see some of the properties associated with a device. Note that the REF property has the value U1 which you gave it in the preceding step. Click on the JEDECFile line and click on OK. When the form appears, enter
in the Value box and click on OK. You should see the filename appear under the GAL16V8A symbol.
- Check the sheet by popping up the banner Check - Sheet menu and choose With defaults. Note any errors specified, then close the Message window and fix any errors you find. (Warnings about dangling nets on two of the GAL16V8A outputs are OK because these two are not used and therefore not connected.)
- Make sure to save a copy of the final version of your sheet.
- Use the banner File menu to print a hard copy of your sheet.
- Close the design architect window, and the "orphan" da command shell window.
SETTING UP THE DESIGN VIEWPOINT
According to the Mentor manual a Design Viewpoint is a set of rules used to establish the configuration of your design. The following sequence of steps will create the proper design viewpoint references for the QuickSimII simulator and the Logic Modeling Corp. models
- In the Design Manager Tools window find the Design Viewpoint Editor(DVE) icon and double click on the icon to open it.
- When the Design Viewpoint Editor window appears, find the OPEN VPT box in the Session window on the right and click on it.
- In the Open design Viewpoint form that appears, enter bcd and click on OK
- Find the SETUP VPT in the Session window on the right and click on it.
- When the menu comes up, select the menu item: Quick_Sim_Fault_Path_Grade, then press OK.
- When the check is completed, pop up the banner File - Save Design Viewpoint menu and choose With same name.
- Quit the Design Viewpoint Editor window. Then put the cursor in the orphan command shell window, hold down the Control key, and press the C key to get rid of this orphan.
SIMULATING THE DESIGN
Whenever you simulate any state machine type circuit such as a counter, shift register, or microprocessor, you must force the machine into a known state at the start of the simulation. This is an important but usually not difficult step. It is often done done by simply asserting a set (preset) or clear (reset) input.
The clr input on your BCD circuit is synchronous which means that you have to assert the clr input high, pulse the clock input high and back low, then bring the clr input low again. Once the state machine is initialized you can clock it to step it through the desired sequence of steps.
- From the Design Manager open QuickSimII. When the form appears, enter /u/your_user_name/bcd as your design pathname, click on Constraint Timing mode, and click on Visible. When the second form appears, in the Timing mode line click on Max then at the bottom of the form click on OK. (Remember, QuickSimII takes a while to get its act together, so be patient.) When the QuickSimII window appears, drag the lower right corner to enlarge it.
- Put the cursor in the main QuickSim window, pop up the QuickSim - Open menu and choose Sheet to display your schematic on the screen. When the sheet window appears, put the cursor in the top box of the window, hold down the left mouse key, and use the mouse to move the sheet to the lower right corner of the QuickSim window.
- Pop up the QuickSim - Add - Traces menu and choose Specified. When the Add traces form appears, click on named signals, enter clk, clr, dir, D, C, B, A, Y, borrow, and carry in the signal name boxes, and click on OK. When the trace window appears, move it to the top of the screen and expand it downward so the all the traces are visible.
- The next task is to generate the force commands which will assert the clk, clr, and dir inputs of the counter. To generate a 10 Mhz clock signal pop up the QuickSim - Force menu and choose Clock. When the form appears, enter clk in the Signal Name box, 100 in the Period box, click on 50% Duty Cycle, click on OK.
To generate a 50 ns wide clear pulse which satisfies the setup and hold times of the GAL16V8A, pop up the QuickSim - Force menu and choose Multiple Values. When the form appears, fill in the blanks to create a pulse for the clr signal which is low for 25 ns, high for 50 ns, and then low.
To generate a signal for the dir input, pop up the QuickSim -Force menu again and choose Multiple Values. When the form appears fill in the blanks to generate a dir signal which is low for 1100 ns and then high.
- Pop up the QuickSim - Run - Simulation menu and choose Until time. Enter 2200 in the Until Time box of the form at the bottom of the screen and click on OK.
- If it is not activated, click on the Trace window to activate it. With the cursor in the Trace window, pop up the QuickSim - View menu and choose All. The entire simulation should now be visible in the trace window.
- Examine the waveforms to see if the counter is sequencing correctly. If the counter is sequencing correctly, zoom in on the display and use the QuickSim - Cursors Add menu to put in some Cursors to accurately determine the propagation delay time between a rising clock edge and an output signal transition. (Remember, if you click on a cursor to select it, you can use the Cursors - slide command to move the selected cursor to a desired position.
- If the sequencing is correct for dir = 0 and dir = 1, make a hard copy of the trace window for the entire simulation.
Assuming that everything worked correctly, the simulation is now complete and you could go home. However, before you go we want to show you one more trick that you will find VERY useful when you are doing multiple iterations of the schematic capture- simulation design cycle.
MAKING AND RUNNING A DO FILE FOR THE ENTIRE SIMULATION
QuickSimII maintains a transcript file which contains a list of the commands you have executed as you ran your simulation. This includes the command you entered to open the sheet window, commands that you entered to open the trace window and add traces, commands that you entered to apply forces, etc. If you save this list of commands in the correct form, you can execute the entire sequence of commands at the start of a new simulation with a single dofile command. Once you have built a do file for a given simulation setup, successive runs are almost automatic. Here's how you do this.
- Pop up the banner MGC - Transcript menu and select Show Transcript - Session to open a window containing a transcript of your sequence of simulation commands.
- Put the cursor on the first letter of the first command, hold the left mouse key down, and use the mouse to move the cursor down the list of commands until you reach the last command. Then release the left mouse key. The commands you have passed over should be highlighted.
- Pop up the banner Edit - Copy to clipboard menu and choose Session.
- Pop up the banner MGC - Notepad menu and choose New.
- Put the cursor in the Notepad window, pop up the Edit - Paste menu and choose Session. This should copy the marked block from the transcript window to the notepad.
- Edit this file so that it is essentially the same as the
attached sample file. Note: the window coordinates will likely be different from those in the example, but this is OK.
- Use the banner File menu to Save the edited file as /u/your_user_name/bcd.do.
- Close the notepad window and then close the transcript window.
- Pop up the QuickSim - Run menu and choose Reset. When the form appears, click on State, click on Setup, and click on OK. When the warning message appears, click on Yes for this demo. NOTE: Normally when you Reset the simulator to time zero to run another simulation within QuickSim as you did in
Tutorial #3, you DO NOT RESET THE SETUP.
- When the QuickSim window is empty, type
and press the Return key. After some time this command should set up the windows, specify traces, apply forces, run the simulation, and show a view of the entire simulation time. From now on, each time you bring up Quicksim on some new version of the bcd design, you can do all this with the single dofile command.
- When you are suitably impressed by what you are now able to do, quit QuickSimII and close its orphan. Quit the Design Manager window and logout of the remote workstation.
GENERATING AND IMPORTING YOUR OWN .JED FILE
As described in another
tutorial, you can use the Cypress Warp2 tools on the unix systems to create a .jed file from a VHDL description. This file can then be "attached" to a GAL device as described above.
If you want to develop the PLD files on a PC computer and import the resultant .jed file into the schematic directory for your Mentor Design. Here's how you do this.
- Logon to one of the computers in the NT lab in the FAB.
- As described in separate tutorials, you can use CUPL or Warp2 to develop the .jed file for your design. Let us call your saved file your_name.jed
- Using the Windows START menu, start the program Ws_ftp (you should be able to find the program at StartÞ ProgramsÞ Windows ApplicationsÞ Ws_ftp).
- When the program opens a Session Properties window will pop up. Make the following entries in the listed fields:
Host Name/Address: ee.pdx.edu
Host Type: Automatic Connect
UserID: your unix logon name
Password: your unix logon password
Then click OK
- In the REMOTE SYSTEM window on the right side of the screen change the directory to
- In the LOCAL SYSTEM window on the left side of the screen change to the directory where your_name.jed is located.
- Select (click the mouse) on the directory entry for your_name.jed
- Click on the right pointing arrow between the REMOTE SYSTEM and LOCAL SYSTEM screen areas to send your_name.jed to the unix system.
- Exit programs and logoff the NT system.
- Login on a Sun workstation and use Mentor's Design architect to link the .jed file to the pld in the schematic as described earlier in this tutorial.