EE171

Electrical Engineering Department
Portland State University
Portland, OR

DESIGN PROJECT #3

Problem Description:

Continuing with Project 1 and 2, you will now implement the design in a PAL (programmable array logic device). Again, a large part of the grade for this project is based on how thoroughly and clearly you document your work.

To complete the project:

  1. Do the WARP Tutorial to learn how to make a .jed file for a VHDL design and how to simulate the .jed file.
  2. Write a rough draft of a VHDL file for your six variable design using the equations derived from your K-maps.
  3. Invoke Galaxy and create a .vhd file as you did in the tutorial. After carefully checking the file, save it as sixvar.vhd. Add comments to the final to explain what the code is doing.
  4. Add sixvar.vhd to the Warp2 Input File list, go to the Options form and choose C16v8, then Compile and Synthesize the design.
  5. If there are syntax errors, edit the .vhd file to correct them, then repeat the Compile and Synthesize. If there are no syntax errors, invoke the Nova simulator.
  6. In Nova, open the sixvar.jed file, generate the stimulus signals, and simulate the circuit as described in the tutorial.
  7. Use your original truth table to determine if the outputs are correct.
  8. If all values are correct, write vectors to the .jed file and write the trace (.psd) file.
  9. Exit from Galaxy.
  10. Print copies of your .vhd, .rpt and .psd files (you could use "enscript -2r -Plw10 file" for these printouts).

Documentation

Your documentation should consist of two separate entities, the log book and the formal report.

Log book

This is an "as you go" write up of the project. Include an ongoing record of your thought process and attempts as you test your design, with DATED ENTRIES. Include a detailed log of the steps you took to simulate and, if necessary, correct the design of the circuit.

Formal report

The formal report is a document that will be written at the end of the project. It will be done "nicely". In fact, think of this as your presentation of the project. It is suggested, but not required, that you type your report. Include the following sections in your report.
    1. Introduction - Describe the problem and your objective for the project.
    2. Discussion - Briefly summarize the process of developing and verifying your VHDL design. Include your .vhd, .rpt, and .psd printouts, labelling anything that you think is unreadable so the reader can easily understand.
    3. Conclusion - What was developed, learned, etc.
    4. Include the following signed "intellectual property" statement:

      I do hereby affirm that I designed this circuit by myself. 
    Signed __________________________________  Date _______________

To receive credit you must do this project yourself and include the signed statement!

Grading: Project 3 is worth 10 points (50 total project points)

Grade will be based 60% on quality of technical work, 40% on quality of documentation.