Electrical Engineering Department
Portland State University
Portland, OR

Description:

In EE271 Design Project #1 you designed and simulated a state machine that used off-the-shelf parts. However, for many real-world designs, off-the-shelf parts and/or simulation models are not available. For these situations, you have to develop models for the desired parts and use the models to produce custom integrated circuits that implement the desired functions. In addition to providing more practice designing a custom state machine, a major objective of this project is to extend your skill with modern design, modeling, simulation, and testing techniques.

For this project you will design a Moore type state machine which asserts an output signal called FOUND when either of two specified serial data bit sequences is detected on an input called SD. After you complete the basic design, you will use the Cypress Warp2 tools to model your design in VHDL and generate a fusemap (.jed) file which will implement your design in a GAL16V8 PLD. To thoroughly test your design, you will first use Mentor's Design Architect to draw a schematic which contains a GAL16V8 PLD and a Pseudo-Random Number Generator such as that in Hall Figure 9-36. Then you will use QuickSimII to simulate the circuit. Note that it is much easier to generate a long sequence of random bits for the SD input with the Pseudo-Random Number Generator than with QuickSimII force commands. Also, PRN generators are useful to have in your "toolkit" because they are often used as part of the Built In Self Test (BIST) circuitry in more complex designs.

Suggested Procedure

1. START A LOG BOOK! See Documentation section for explanation.
2. Draw a block diagram for the sequence detector state machine showing inputs and outputs.
3. Carefully draw and check a state (bubble) diagram for a machine that will detect either of the sequences assigned to you. Note that the sequences may overlap. Check the response of your state diagram with several random bit patterns to make sure each pattern takes the correct path through the state diagram.
4. Next you want to translate your bubble diagram to VHDL. The attached example should help you see how to do this. (For further examples, look in the unix system directory/pkgs/warp2+/examples/fsm.) To generate your source file, you can use the Warp2 editor as described in the Cypress Warps2 tutorial, or you can use some other ASCII editor such as textedit, emacs, etc. Make sure to use a .vhd extension as part of your filename and make sure to include a Reset input in your design so you can put the device in a known state at the start of a simulation.
5. Check your file carefully. Make sure each "if" clause has a corresponding "end if", each "case" statement has a corresponding "end case", check semicolons, etc. Then compile your VHDL source file as described in the Cypress Warp2 tutorial and note any errors indicated.
6. Carefully read your source file and use the error messages to help you find errors. Note that the error messages are often not too helpful and that a small error in a line near the start will often cause many error messages. For this reason, after you find and fix an error, reload and recompile the file.
7. Repeat the edit/compile cycle until the file compiles with no errors, then synthesize the design for a 16V8 as described in the Warp Tutorial.
8. The next step is to use the NOVA simulator to do a preliminary check on whether the design works correctly or not. Before you bring up the Nova simulator, on paper sketch out waveforms for the reset signal, the clock signal, and for a data bit sequence which tests the two main paths through your bubbles diagram. Writing these down is much more efficient and less error prone than trying to make up the wave forms out of your head and enter them directly into the simulator.
9. Bring up the simulator, apply the stimulus signals you worked out, and run the simulation. If the results are correct, write the .jed and the .psd files, then exit Warp2. You now have a .jed file that could be used to program an actual GAL16V8 device. It can also be used to "program" a GAL16V8 device in a Design Architect based design. The following section describes how you do this and how you thoroughly test your design.
10. If you have not already done so, work your way through Mentor Tutorial #4 to gain further skill with the Mentor tools and learn how to work with a design containing a PLD.
11. The circuit that you will develop in Design Architect will contain two major components, a Lattice GAL16V8-25 (LMC library, Lattice, 20-pin PALs) for your state machine, and a pseudo random number generator (PRNG) to supply a stream of bits for testing your circuit. You have two choices as to how you implement the PRNG:
    Choice #1: Use Design Architect to draw a schematic that contains the Pseudo-Random Number Generator in Hall Figure 9-36.
    Choice #2: Model the Figure 9-36 circuit in VHDL, develop the .jed file for it and use another GAL16V8A to implement the PRN Generator in your Design Architect schematic.
    Choose one of these two methods.
12. Use Design Architect to draw a schematic that contains the Pseudo-Random Number Generator (either a PAL or a circuit made from components, per your choice in step 10) and the Lattice GAL16V8-25 (LMC library, Lattice, 20-pin PALs) for your state machine. Note that the Most significant Q from the PRNG should be connected to the SD input of your 16V8 to supply a serial bit stream to your sequence detector. Make sure to include a reset input so that you can put the PRNG and the state machine in known states.
13. Attach your .jed file(s) to the GAL16V8A device(s) as described in Mentor Tutorial #4.
14. Check and save your design in Design Architect.
15. Invoke DVE on the design to create a viewpoint. Check and save the viewpoint in DVE.
16. Use QuickSimII to simulate your design. Note that because the PRN generator supplies the serial bit pattern to SD, you simply have to apply forces to reset and clock.
17. Carefully check that the FOUND signal is asserted for the desired sequence of data bits and is not asserted for any other sequences. If all is correct, print a copy of the simulation waveforms for your logbook.

Sequence

You will be assigned two of the following sequences to detect:

PSU STUDENTS CHECK HERE FOR YOUR ASSIGNED SEQUENCE

Documentation

The documentation package that you will submit must consist of two separate entities, your log book and your written report.

Log Book

Your logbook should be your "daily diary" of progress as you work through this project. In the log book you should document your thought process and keep record of your progress. Maintain dated entries. In the early stages of the project, you may want to outline your plan of attack and record it in the log book so that you can refer to it. You may want to include data sheet copies in your log book so that you can easily refer to them when needed. If you identify important design considerations, record them in the log book. You should keep your log AS YOU GO -- don't try to write up a log after you've finished the project. Such log books are kept by many engineering professionals on the job. Indeed, many companies require that log books be kept by technical employees. If you're unfamiliar with the concept of a logbook and have questions please see your instructor or TA.

Report

Your report should summarize your work. Some of the possible sections for your report are shown below, along with some key items that you should include along with the text of the report.

Statement of Problem

Design of State Machine Design and Pseudo Random Number Generator

• Block diagram for FSM
• State diagram for FSM
• VHDL Code for FSM
• Waveform(s) from WARP pre-testing of FSM
• VHDL Code for PRNG (if implemented with VHDL)
• Waveform(s) from WARP pre-testing of PRNG (if implemented with CHDL)

Simulation

• Mentor Schematic
• QuickSim output (labeled as necessary so the reader can understand!) showing correct detection of each occurrence of target bit sequences. Your waveform should show results for at least 100 bits from the serial data stream.

Summary

• What did you learn?
• Comments regarding performance of your design

Signed intellectual property statement shown below

• I, ________________ affirm that I designed and implemented this project by myself.

Grading

Your project will be graded as follows:

• 60% - Quality of technical work.
• 40% - Quality of documentation (report and logbook)