Electrical Engineering Department
Portland State University
Portland, OR

Description

The objective of this exercise is to design and test a simple 3-bit counter type state machine which steps through a specified sequence of states correctly at the highest frequency possible with the Motorola MECL 10KH family parts available in the Logic Modeling Corporation library. You will be assigned a specific state sequence by your instructor.

In addition to a clock input the circuit must have a DIR (sequence DIRection) input. If the DIR input is low, the counter should step to the NEXT state in the specified sequence when clocked (i.e., "left to right" in your state sequence list). If the DIR input is high, the counter should step to the PREVIOUS state in the specified sequence (i.e., "right to left"). The circuit must operate correctly for a temperature range of at least 0 degrees C to 70 degrees C.

You will actually be designing both a D flip-flop based design and a JK flip-flop based design so you can compare the predicted performance of the two. You will then select one of the two designs based on predicted performance and then use the Mentor tools to draw a schematic for and simulate the design.

Suggested Procedure

1. START A LOG BOOK! See Documentation section for explanation.
2. If you do not have experience using the Mentor Graphics tools, it is recommended that you work your way through the Mentor Tutorials available on the EE 271 main web page.
3. Think carefully about how the counter is supposed to operate and draw a block diagram showing input, outputs, and next state decoder.
4. Draw a state diagram or ASM chart for the counter. Write a next-state/excitation table for the design assuming D flip-flops. Write a next-state/excitation table for the design assuming J-K flip-flops.
5. In the Reserve Library, skim through the introductory sections of the Motorola MECL Device Data book to get an overview of the ECL family. Do not get lost in the details. Focus on the following sections: Power Supply; Unused Inputs; Circuit Interconnections.
6. Find the data sheets for available J-K and D flip-flops and combinational logic gate devices and copy them for future reference.
7. Before proceeding to the detailed design, think about design parameters that will effect the maximum operating frequency of your circuit. What types of things will limit speed? How can you minimize the effect of these limiting factors?
8. Use Karnaugh maps to develop the excitation equations for a D flop-flop design and the excitation equations for a J-K flop-flop design as described in Hall Chapter 12.
9. On one of the Sun Computers, bring up the Mentor Design Architect as described in Mentor tutorial #2 and open a sheet called test.
10. In the banner Libraries menu select Logic Modeling Corp. When the LMC library list pops up in the right window, select General Purpose Logic -flip-flops - Motorola. Write down the available D or J-K flip-flops parts that have numbers which begin with 10H1. (Note: parts such as 10H531 are military temperature range versions of the 10H131). Also locate available combinational logic gate devices in the 10H family. Models may be available for all the devices listed in the MECL Device Data book, and you will have to use parts that are available in the LMC library.
11. Based on the information that you have gathered and the design considerations developed in Step 7, choose either D or J-K flip flops for your circuit and design the next state decoder. If you are not sure which flip flop type to use you may design and simulate circuits for both types, but this approach will obviously require more time.
12. Calculate the predicted maximum operating frequency for your design.
13. With Mentor Graphics Design Architect, draw a complete circuit for your design. Note: in anticipation of simulating your design using QuickSim II, you will probably want to provide PORTIN connectors for a clock, the DIR input, and a RESET signal to put your state machine into a known state.
14. Using QuickSim II, simulate the circuit with a 10 MHz clock to determine if the count sequence is correct for DIR low and DIR high. If not, find the problem and fix it.
15. When the logic of the circuit is correct, begin decreasing the clock period and re-simulating until your circuit no longer works correctly. Identify the maximum operating frequency for your circuit. If the maximum operating frequency is different than you predicted in step 12 try to determine why. Perhaps there is a problem in your circuit? Maybe the parameters that you used in your prediction are different than those implemented in QuickSim II?
16. When everything works right and you are comfortable with your design pat yourself on the back and move on to putting together your documentation package.

Documentation

The documentation package that you will submit must consist of two separate entities, your log book and your written report.

Log Book

Your logbook should be your "daily diary" of progress as you work through this project. In the log book you should document your thought process and keep record of your progress. Maintain dated entries. In the early stages of the project, you may want to outline your plan of attack and record it in the log book so that you can refer to it. You may want to include data sheet copies in your log book so that you can easily refer to them when needed. If you identify important design considerations, record them in the log book. You should keep your log AS YOU GO -- don't try to write up a log after you've finished the project. Such log books are kept by many engineering professionals on the job. Indeed, many companies require that log books be kept by technical employees. If you're unfamiliar with the concept of a logbook and have questions please see your instructor or TA.

Report

Your report should summarize your work. Some of the possible sections for your report are shown below, along with some key items that you should include along with the text of the report.

Statement of Problem

Description of Design

• Block diagram
• State diagram
• Next state tables
• K-maps
• Simplified Boolean expressions for next state decoder
• Basis for design decisions
• Performance (operating speed) estimate

Design Validation (Simulation)

• Mentor Schematic
• QuickSim output (labeled as necessary so the reader can understand!) showing correct sequencing for DIR low and DIR high.
• QuickSim output illustrating maximum operating speed.

Summary

• What did you learn?
• Comments regarding performance of your design

Signed intellectual property statement shown below

• I, ________________ affirm that I designed and implemented this project by myself.

Grading

Your project will be graded as follows:

• 60% - Quality of technical work (including how the operating speed of your design compares to that achieved by others in the class)
• 40% - Quality of documentation (report and logbook)

Count Sequences

The first letter of your last name determines the count sequence:

To receive credit you must do this project yourself