EE 271 - DIGITAL SYSTEMS
MIDTERM 1
Examples of problems
Problem 1. Group A.
Design a state machine, using JK flip-flops that accepts even number of ones,
separated with odd number of zeros.
Solution.
The formulation of the problem
suggests clearly that only sequences that start and terminate with 1 are accepted.
Each such sequence should have 2, 4, 6, 8, 10.... ones.
Every two ones should be separated by 1, 3, 5, 7, 9, ..... zeros.
We assume that each sequence starts from the "1", and whenever the sequence is recognized
as "correct", an output of "1" is given. It may be however possible that this sequence
is a part of another longer sequence, then each sequence should be detected and
signalized with bit "1" at the end of the correct sequence.
Example
101010001 = INPUT ,
001000001 = OUTPUT, because each time there was an even number of ones, separated by odd number of zeros.
The accepted sequences are then
101, 10001, 1 1,.....
1010101, 101000101, 10101 1,.....
10101000001, 101010001, 101000001000001,.....
As we see, initial zero leads to a state that none of the sequences will be accceptable.
Thus, the following Mealy table can be created:
P.S. \ X 0 1
-------------------------
1 6,0 2,0
2 3,0 6,0
3 2,0 4,1
4 5,0 6,0
5 4,0 2,0
6 6,0 6,0
---------------------------
N.S./output
The procedure of realizing this state table with JK flip-flops is standard,
and was explained several times in class and in additional meetings.
Problem 1. Group B.
Design a state machine, using JK flip-flops that accepts even number of zeros,
separated with odd number of ones.
Solution.
This is very similar to the problem for Group A.
The sequences accepted are 010, 01110, 0111110, .... 010101110 etc.
The table is the same as before, headings of colums for X=0 and X=1 are just swapped.
P.S. \ X 1 0 <<< observe swapped symbols of X
-------------------------
1 6,0 2,0
2 3,0 6,0
3 2,0 4,1
4 5,0 6,0
5 4,0 2,0
6 6,0 6,0
---------------------------
N.S./output
Problem 2. Group A.
Design a circuit with 6 stages that will execute the operations
1) Johnson counter
2) Binary counter
3) shl non-cyclic
4) shr non-cyclic
Solution.
The circuit is a combination of standard generalized register, with 6 stages,
with a binary counter.
Each stage has a MUX with 2 address inputs, A and B,
that select one of four data inputs. Output of each MUX
goes to the D input of D type flip-flop.
Let us assume the following encoding of operations.
A B
00 Johnson counter
01 Binary counter
10 shl non-cyclic
11 shr non-cyclic
Then data input 0 of MUXs will realize Johnson counter.
All of them, except the first one, are connected to Q output of previous FF.
The data input 0 in the first MUX is connected to the \bar{Q} of the last FF.
The input data 2 corresponds to the shl non-cyclic operation.
Thus MUX_i has on input data 2 the value of Q_{i+1}.
The last MUX_i, which is MUX_6, has a separate input called SERIAL_SHIFT_LEFT_DATA_IN
The input data 3 corresponds to the shr non-cyclic operation.
Thus MUX_i has on input data 2 the value of Q_{i-1}.
The first MUX_i, which is MUX_1, has a separate input called SERIAL_SHIFT_RIGHT_DATA_IN.
The most complex it is to design the binary counter.
But, we designed a binary counter in class, where, using our new enumeration
scheme with 6 stages, we had:
D_6 = Q_6 EXOR 1
D_5 = Q_5 EXOR Q_6
D_4 = Q_4 EXOR Q_5 Q_6
Thus, the above function should be put to data 1 inputs of the MUXes, MUX_6, MUX_5, and MUX_4,
respectively.
Generalizing the above equations for more flip-flops, we obtain the following
D_3 = Q_3 EXOR Q_4 Q_5 Q_6
D_2 = Q_2 EXOR Q_3 Q_4 Q_5 Q_6
D_1 = Q_1 EXOR Q_2 Q_3 Q_4 Q_5 Q_6
Thus, the total set of equation for data input 1 in MUX-es becomes:
D_6 = Q_6 EXOR 1
D_5 = Q_5 EXOR Q_6
D_4 = Q_4 EXOR Q_5 Q_6 = Q_4 EXOR Q_5 C_5 where C_5 = Q_6
D_3 = Q_3 EXOR Q_4 Q_5 Q_6 = Q_3 EXOR Q_4 C_4 where C_4 = Q_5 Q_6
D_2 = Q_2 EXOR Q_3 (Q_4 Q_5 Q_6) = Q_2 EXOR Q_3 C_3, where C_3 = Q_4 Q_5 Q_6
D_1 = Q_1 EXOR Q_2 (Q_3 Q_4 Q_5 Q_6) = Q_1 EXOR Q_2 C_2, where C_2 = (Q_3 Q_4 Q_5 Q_6) = Q_3 C_3.