Problems from Exam

PROBLEM 1.

Given is Finite State Machine from Figure 1.

A) Minimize this machine to the minimum number of states.
   How many solutions did you find?

B) For the minimized machine, or one of them,
find the optimum state assignment. You can use any of
the several state assignment (encoding)
methods from class or from the Kohavi or Hachtel books,
but you must clearly tell which method you use, and what you
are supposed to optimize using this particular method.
Your selected assignment method should assume D flip-flops.

C) Find the best assignment for JK flip-flops.
You can either use the method from the class, or adapt any
D type based method that you know to be used with JK flip-flops.
Make an argument, why this method is good?
If you are using the class method, make a point,
what is this method trying to minimize and why? 
What is the difference of assigning state machine for 
D flip-flops, for T flip-flops, and for JK flip-flops.

D) Realize the circuit from p. B) with D flip-flops
and multiplexers. You cannot use other gates.

E) Realize the circuit from p. C) with JK flip-flops,
Positive Davio Gates (which realize the function f = (a AND b) EXOR c) 
and inverters. You cannot use other gates.


PROBLEM 2.

You know the behavior of synchronized D flip-flop
with data input D and clock input C.
Assume that this flip-flop operates from the falling slope of C.
Internally the D flip-flop is an asynchronous circuit with two inputs,
C and D, and two outputs Q and Qbar.
Using the methods of designing asynchronous circuits,
design the D flip-flop from only NAND gates.
Remember about phenomena like hazards and races.
remove all dangerous occurences of them by only logical design.
You do not want to have a dynamic hazard in the outputs, either.
Minimize the total number of inputs to NAND gates.
Verify your work: draw the timing diagram and verify your Karnaugh maps.


PROBLEM 3.

Using only NOT, AND and  OR gates, find a regular structure that realizes
the function specified as follows.
In addition, all connections between gates, other than input variables,
must be local and short.
Draw your solution on a rectangular grid to show that all connections
are local and short.

The circuit has 5 inputs and 3 outputs. The three-bit number on the outputs
X, Y, Z, is equal to the number of input signals that are equal one.
For instance if there are any three inputs equal one,
then the output will be Xbar, Y, Z.
With any four inputs equal one, the output will be X, Ybar, Zbar.

What is the basic property of this function?
Do you remember any logic equalities or design
methods for such functions? Write them and verify.
Remember, that your structure MUST be regular.