SYSC5603 = (ELG6163) Digital Signal Processing Microprocessors, Software and = Applications

SYSC5603 (ELG6163) Digital Signal Processing=20 Microprocessors, Software and Applications

References

Books

[Ackenhusen99] J. G. Ackenhusen, Real-time=20 Signal Processing: Design and Implementation of Signal Processing = Systems,=20 Prentice Hall, 1999. =

[Constantinides04] G. A. Constantinides, P. Y. K. Cheung, W. Luk, Synthesis and Optimization of DSP=20 Algorithms, Academic Publishers, 2004.

[Chassaing05] R. Chassaing, Digital=20 Signal Processing and Applications with the C6713 and C6416 DSK, = John Wiley=20 & Sons, 2005.

[Kester03]=20 W. Kester, Mixed-Signal=20 and DSP Design Techniques, Analog Devices, Newnes,=20 2003.

[Kuo05] S.=20 M. Kuo, W. S. Gan, Digital Signal Processors:=20 Architectures, Implementations, and Applications, Prentice Hall,=20 2005.

[Lapsley97] P. Lapsley, = J. Bier, A.=20 Shoham, E. A. Lee, DSP Processor = Fundamentals:=20 Architecture and Features, IEEE Press, 1997.

[Meerbergen] J.=20 van Meerbergen, Embedded Multimedia = Systems in=20 Silicon, http://www.ics.e= le.tue.nl/~jef/education/5p520/,=20 Technology Eindhoven, Department ICS, Division ES.

[Meyer04] U. Meyer-Baese, Digital Signal = Processing with=20 Field Programmable Gate Array, Springer-Verlag,=20 New York, 2004.

[Mitra06] S. K. Mitra, Digital Signal Processing, A Computer-Based approach, McGraw Hill, = 2006.

[Oppenheim98] A. V. Oppenheim, R. W. Schafer, Discrete-time signal = processing, 2nd=20 edition, Prentice Hall, 1998.

[Parhi 99] K. K. Parhi, VLSI Signal Processing Systems, = Design and=20 Implementation. John Wiley & Sons, Inc., New York, 1999. Slides

[Shenoi06] B. A. Shenoi, Introduction=20 to Digital Signal Processing and Filter Design, John Wiley & = Sons, Inc.,=20 2006.

[Smith97] S. Smith,=20 The Scientist and = Engineer's Guide=20 to Digital Signal Processing,=20 California=20 Technical Publishing, 1997.

[Sriram00] S. Sriram, = S. S.=20 Bhattacharyya, Embedded = Multiprocessors:=20 Scheduling and Synchronization, Marcel Dekker Inc., 2000.

[Wanhammar99] Lars Wanhammer, DSP=20 Integrated Circuits, Academic Press, San Diego, 1999.

Journal=20 papers

[Adams04] L. Adams, =93Semiconductor options for = real-time=20 signal processing,=94 EDN, November 25, 2004, p. 87-94.

[Allen05]=20 R. Allen, =93Compiling high-level languages to = DSPs: automating the implementation=20 path,=94 IEEE Signal = Processing Magazine, Vol. 22, = no=20 3,=20 pp. 47-56,=20 2005. =

[Bondalapati00] K.=20 Bondalapati, V. K. Prasanna, Reconfigurable Computing: = Architectures,=20 Models and Algorithms=20 (PDF),Current Science: Special Section on Computational = Science 78(7),=20 April 2000.

[Cravotta05] R.=20 Cravotta,=94 EDN 2005 DSP = Directory: Targeted=20 DSPs take aim,=94 EDN, = 2005.

[Duhamel90] P. Duhamel, M. Vetterli, =93Fast Fourier Transform: A tutorial = review and a=20 state of the art=94, Signal Processing 19, pp. 259-299, 1990

[Eyre00] J. Eyre, and J. Bier, "The = evolution of=20 DSP processors," IEEE Signal Processing magazine, March 2000, vol. = 17, no.2,=20 pp. 43-51.

[Fridman00] J. Fridman, = "Sub-word=20 parallelism in digital signal processing -- applying the TigerSHARC architecture," IEEE Signal = Processing=20 Magazine, vol. 17, no. 2, pp. 27-35, March 2000.

[Guerra96] = L. M. Guerra,=20 Behavioral Level Guidance Using Property-Based Design = Characterization,=20 Ph.D. thesis, Berkeley, 1996.

[Hu92] Y. H. Hu, =93CORDIC-base= d VLSI=20 architecture for digital signal = processing,=94 IEEE=20 Signal Processing Magazine, July 1992, pp. 16-35.

[Jerraya04] A.A. Jerraya, W. Wolf,=94=20 The=20 What, Why, and How of MpSOCs,=94 from = Multiprocessor=20 Systems-on-Chips, Morgan Kaufman, 2004

[Kumar05] R. Kumar, D. M. Tullsen, N.P. Jouppi, = P. Ranganathan, =93Heterogeneous=20 Chip Multiprocessors,=94 IEEE Computer, Volume: = 38, Issue: 11, pp. 32-38, 2005.

[Li03] W Li, Studies = on implementation = of low power FFT=20 processors, Thesis, Link=F6pings University, 2003

[Liu71] B. Liu, =93Effect=20 of Finite Word Length on the Accuracy of Digital Filters - A = Review,=94=20 IEEE Trans. on Circuit Theory, Vol. 18, No 6, Nov. 1971

[McFarland88] Michael C. McFarland, Alice C. = Parker, Raul=20 Camposano, "Tutorial=20 on high-level synthesis", Proceedings of the 25th ACM/IEEE = conference on=20 Design automation, pp. 330-336, June 1988.

[Moretti05] G.=20 Moretti,=94 Design complexity = requires=20 system-level design,=94 EDN, 2005.=20

[Parker96]=20 D.A. Parker, K.K. Parhi=20 , = =93Area-efficient parallel FIR = digital filter=20 implementations,=94 Proceedings of International Conference = on=20 Application = Specific=20 Systems, Architectures and Processors, 1996. ASAP = 96.=20

[Parhi89] K.K.=20 Parhi,=20 =93Algorithm transformation techniques for concurrent = processors,=94 Proc. IEEE, vol. 77(12), pp. 1879=961895, = December 1989.

[Parhi89_2] K.K.=20 Parhi=20 and D.G. Messerschmitt, =93Pipeline interleaving and parallelism in recursive digital filters,=94 IEEE Trans.=20 Acoustics, Speech, Signal Processing, vol. 37(7), pp.=20 1099=961135, July 1989.

[Parhi92] K. K.=20 Parhi, C.-Y. Wang, and A. P.=20 Brown, =93Synthesis=20 of control circuits in folded pipelined DSP architectures,=94 = IEEE J.=20 Solid-State Circuits, vol. 27, pp. 29-43, Jan.=20 1992.

[Parhi95] K. K. Parhi, High-level algorithm and =
architecture transformations for DSP synthesis, The Journal of VLSI =
Signal Processing, Vol 9, pp 121-143, =
1995

[Richards04]=20 M. A. Richards, and G. A. Shaw, "Chips,=20 Architectures and Algorithms: Reflections on the Exponential Growth of = Digital=20 Signal Processing Capabilities," Submitted to IEEE Signal Processing = Magazine, 2004

[Rabay98]=20 J. M. Rabay et al (Ed.), = =93VLSI=20 Implementation Fuels the Signal Processing Revolution,=94 IEEE = Signal=20 Processing Magazine, Jan. 1998.

[Seshan98]=20 N. Seshan, =93High=20 VelociTI Processing,=94 IEEE Signal = Processing Mag, March 1998, pp. 86-101 (Tutorial on TMS320C6000 VelociTI=20 Advanced VLIW Architecture)=20

[Sung95]=20 W. Sung, K. Kum, =93Simulation Based = Word Length=20 Optimization Method for Fixed-Point Digital Signal Processing=20 Systems,=94=20 IEEE Trans. Signal=20 Processing, vol.=20 43, pp. 3087 -- 3090, Dec. 1995.

[Thiele05] L.=20 Thiele, E. Wandeler; S. Chakraborty, =93Performance analysis = of=20 multiprocessor DSPs: a stream-oriented component = model,=94=20 IEEE=20 Signal Processing Magazine, = Vol. 22, no=20 3,=20 pp. 38-46,=20 2005.

<= /A>

<= SPAN=20 style=3D"COLOR: windowtext; TEXT-DECORATION: none; text-underline: = none">[White89] S.=20 A. White, "Applications of distributed arithmetic to digital = signal=20 processing: a tutorial review," IEEE ASSP Magazine, = Vol. 6,=20 no. 3 , July 1989, pp. 4 = -19.

[Wiangtong05]=20 T. Wiangtong, P.Y.K. Cheung, W. Luk, =93Hardware/software = codesign: a=20 systematic approach targeting data-intensive = applications,=94=20 IEEE=20 Signal Processing Magazine, = Vol. 22, no=20 3,=20 pp. 14-22,=20 2005.

Other=20 documents

[Lall05]=20 N. Lall, =20 E. Cigan, = =93Plug and Play Design = Methodologies for=20 FPGA-based Signal Processing,=94 FPGA=20 and Programmable Logic Journal, 2005.=20

[Philips]=20 Philips Semiconductors, =93An Introduction To Very-Long Instruction Word = (VLIW)=20 Computer Architecture.=94

[AlteraDSP] Altera, = DSP Literature, = 2005.

Interesting=20 courses and sites

[Brodersen03-Slides]=20 R.W. Brodersen EECS 225C VLSI Signal Processing, Course = notes,=20 Berkeley, 2003.

[Dahnhoun02-Slides]=20 N. Dahnhoun, 31611 Real Time Signal = Processing, Slides=20 for the TMS320C6000 Teaching ROM, = Bristol=20 University, 2002.=20

[DSPPrimer-Slides] The=20 DSPforFPGAs = Primer,=20 University of Strathclyde, Scotland, UK, = August 2005.=20

[Hsiung05-Slides]=20 Pao-Ann Hsiung, <= SPAN=20 style=3D"COLOR: blue">SoC Design Flow and Tools, = Course notes,=20 National Chung Cheng University, Taiwan, 2005.

[Hu04-Slides] Yu Hen=20 Hu, ECE 734 VLSI Array Structures for Digital Signal=20 Processing, Course notes, University=20 of Wisconsin, 2004.

[Meerbergen-Slides]=20 J. van Meerbergen, Embedded Multimedia Systems in Silicon, http://www.ics.ele.tue.nl/~jef/education/5p520/, = Technology Eindhoven, Department ICS, Division ES.

[Takala05]=20 J. Takala, TKT-3516 Signal Processors, = Lecture=20 slides, Tampere University of Technology, =20 2005.

[Verbauwhede00-Slides] Ingrid Verbauwhede, EE213A=20 Advanced Digital = Signal=20 Processing Circuit Design,=20 Course notes, UCLA, 2000.

Implementing DSP Designs in = FPGAs, Altera Labs, System On = A Chip=20 Research Group, University of New Brunswick.