FUNCTIONAL DECOMPOSITION OF BOOLEAN FUNCTIONS BASED ON
INFORMATION RELATIONSHIP MEASURES
by Artur Chojnacki, Technical University of Eindhoven, Eindhoven, The Netherlands.
The opportunities created by modern microelectronic technology cannot
be fully exploited, because of weaknesses of the traditional logic
synthesis methods applied in the most todays commercial CAD tools.
Particularly in the case of (C)PLDs, look-up table (LUT) based FPGAs
and complex CMOS-gates, the constraints are imposed not on the function
type a certain logic building block can implement, but on various
blocks structural parameters (e.g. the maximum number of the blocks
inputs, outputs etc.) and on interconnections between the blocks.
A logic block is able to implement any function with limited dimensions.
On the other hand, the traditional logic synthesis methods do not
consider hard structural constraints and are devoted to only some
very special cases of possible implementation structures involving some
minimal functionally complete systems of logic operators (e.g. AND+OR+NOT).
They require a post synthesis technology mapping for another implementation
structures. If the actual synthesis target strongly differs from one of
these minimal systems, e.g. involves a lot of complex gates, look-up table
FPGAs or (C)PLDs, any technology mapping cannot guarantee a good result,
because the initial synthesis is performed without close relation to the actual
target. Therefore, there is presently much research in the field of general
Functional decomposition consists of breaking down a complex system of discrete
functions or relations into a network of smaller and relatively independent
co-operating sub-functions (sub-relations), in such a way that the original
systems behavior is preserved, some constraints are satisfied and some
objectives are optimized. A sub-function (sub-relation) in the network can be
any sort of function (relation) satisfying certain specific structural
A new bottom-up multi-level logic synthesis method for LUT-based FPGAs will
be presented. It is based on the theory and methodology of general decomposition
which allow for modeling of all possible circuits structures, and efficiently
finding some (near-)optimal circuit structures in a heuristic search.
The method implements a bottom-up synthesis process: the circuit is built level
by level from inputs to outputs. It uses information relationship measures for
design decision making in the scope of the heuristic search for solutions.
This limits the solution search space to a manageable size while keeping the most
promising solutions in the limited space. The experimental results of the prototype
tool that implements the method demonstrate that its application results in very
effective circuits for symmetric functions. Results for asymmetric functions are
also very good.
Artur Chojnacki received his M.Sc. in Computer Science from
Warsaw University of Technology in 1992.
From 1992 to 1997 he worked at ZWUT S.A. a Siemens Company as a
Quality Assurance Engineer, Software Team Leader and Project Leader.
Currently he is Ph.D. student in the Department of Electrical
Engineering at the Eindhoven University of Technology, The Netherlands,
working unders supervision of Professor Lech Jozwiak.
He performs research in the area of logic synthesis for look-up table
based (LUT) field programmable gate arays (FPGAs).